S28HL01GTFPBHA030
on request

S28HL01GTFPBHA030

Datasheet
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S28HL01GTFPBHA030
S28HL01GTFPBHA030
Datasheet


Product details

  • Classification
    ISO 26262-compliant
  • Density
    1024 MBit
  • Family
    HL-T
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    166 / 166
  • Interfaces
    xSPI (Octal)
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Planned to be available until at least
    2037

OPN
Product Status on request
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-22282)
Packing Size 2600
Packing Type TRAY
Moisture Level N/A
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant No

Product Status on request
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-22282)
Packing Size 2600
Packing Type TRAY
Moisture Level -
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S28HL01GTFPBHA030 is a 1 Gb (1024 Mbit) SEMPER™ HL‑T NOR flash for code storage and functional-safety systems. It operates from 2.7 V to 3.6 V and uses an xSPI (octal) interface with 166 MHz SDR/DDR, delivering up to 333 MByte/s bandwidth. ISO 26262‑compliant features include SECDED ECC, interface CRC, data integrity CRC, SafeBoot, and Endurance Flex wear leveling. Planned availability is at least 2037.

Features

  • 45-nm MIRRORBIT™ stores 2 bits/cell
  • Uniform or hybrid sector architecture
  • 256 or 512-byte program buffer
  • 1024-byte OTP secure silicon array
  • Octal 8S-8S-8S and 8D-8D-8D
  • JEDEC JESD251 xSPI compliant
  • Data strobe (DS) for read capture
  • ECC on 16-byte units, SECDED
  • SafeBoot status detects init faults
  • AutoBoot outputs data after reset
  • LBP and ASP sector protection
  • Hardware or software reset support

Benefits

  • Higher density with fewer cells
  • Fits boot code and data layouts
  • Faster page program transactions
  • Stores IDs and secrets securely
  • High throughput on few signal pins
  • Easier host support via xSPI
  • Improves timing margin at high speed
  • Reduces bit errors in stored code
  • Enables recovery after bad power-up
  • Cuts boot time and host firmware steps
  • Prevents unauthorized code changes
  • Simplifies robust system reset design

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Design resources

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