S27KL0642DPBHV023
Active and preferred
RoHS Compliant
Lead-free

S27KL0642DPBHV023

Data Sheet
package

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S27KL0642DPBHV023
S27KL0642DPBHV023
Data Sheet

Product details

  • Density
    64 MBit
  • Family
    KL-2
  • Initial Access Time
    36 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S27KL0642DPBHV023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S27KL0642DPBHV023 is a 64 Mb HYPERRAM self-refresh DRAM (PSRAM) with HYPERBUS interface, 8-bit DQ and RWDS, in a 24-ball FBGA. DP speed grade supports DDR transfers up to 166 MHz clock with 35 ns max access time and wrapped or linear burst options. It operates from 2.7 V to 3.60 V VCC over -40C to +105C (B grade) and provides Hybrid Sleep and deep power-down down to 15 A at 105C.

Features

  • HYPERBUS™ interface
  • 1.8 V or 3.0 V I/O support
  • Single-ended or diff clock option
  • 8-bit DDR data bus (DQ[7:0])
  • RWDS strobe and write data mask
  • Optional DCARS read strobe
  • 200 MHz maximum clock rate
  • Up to 400 MBps data throughput
  • Max access time (tACC) 35 ns
  • Hybrid sleep retains data
  • Deep power-down stops refresh
  • ESD: 2 kV HBM, 500 V CDM

Benefits

  • Fast MCU memory expansion over x8
  • Works with 1.8 V or 3.0 V rails
  • Clock options ease PCB constraints
  • DDR x8 reduces routing complexity
  • RWDS improves DDR timing margins
  • DCARS widens read data eye margin
  • 200 MHz supports high bandwidth I/O
  • 400 MBps enables fast frame buffers
  • 35 ns tACC reduces access latency
  • Hybrid sleep saves power, keeps data
  • DPD minimizes power when data not needed
  • High ESD improves handling robustness
Documents

Design resources

Partner solutions

Developer community

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