S27KL0641DABHB020

S27KL0641DABHB020

Data Sheet

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S27KL0641DABHB020
S27KL0641DABHB020
Data Sheet

Product details

  • Bus Width
    x8
  • Density
    64 MBit
  • Family
    KL-1
  • Initial Access Time
    40 ns
  • Interface Bandwidth
    200 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 100
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Technology
    HYPERRAM
OPN
Product Status
Infineon Package
Package Name
Packing Size
Packing Type
Moisture Level
Moisture Packing
Lead-free
Halogen Free
RoHS Compliant
Infineon stock last updated:
The S27KL0641DABHB020 is a 64 Mb (8 MB) HyperRAM™ self-refresh DRAM with a low-signal-count interface (11 signals), 8-bit DDR data bus, and RWDS strobe/mask. It supports up to 100 MHz clock (200 MBps) at 3.0 V VCC/VCCQ (2.7 V to 3.6 V) with configurable wrapped or linear bursts. The DABHB020 option is a 24-ball 1.00 mm-pitch FBGA (6×8×1.0 mm), AEC-Q100 Grade 2 (-40 to +105°C), tray-packed device.

Features

  • HyperRAM low-signal-count interface
  • 8-bit DDR data bus (DQ[7:0])
  • 11/12 interface signals (VIO)
  • Up to 166 MHz clock at 1.8 V
  • Up to 100 MHz clock at 3.0 V
  • Up to 333 MBps peak bandwidth
  • RWDS strobe with mask function
  • Wrapped burst 16/32/64/128 bytes
  • Linear and hybrid burst options
  • Deep Power Down mode (DPD)
  • 1.7 V to 1.95 V supply range
  • 2.7 V to 3.6 V supply range

Benefits

  • Cuts MCU pin count vs parallel DRAM
  • DDR boosts throughput per clock
  • Simplifies routing with fewer traces
  • 166 MHz supports fast memory reads
  • 100 MHz fits 3.0 V host designs
  • 333 MBps supports rich HMI assets
  • RWDS eases timing, masks writes
  • Burst options optimize bus efficiency
  • Linear bursts fit streaming access
  • DPD reduces standby power drain
  • Wide 1.8 V supply eases power tree
  • Wide 3.0 V supply fits legacy rails
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