Active
RoHS Compliant
Lead-free

S26KS128SDGBHM030

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S26KS128SDGBHM030
S26KS128SDGBHM030
Data Sheet

Product details

  • Bus Width
    x8
  • Classification
    ISO 26262-ready
  • Density
    128 MBit
  • Family
    KS-S
  • Initial Access Time
    96 ns
  • Interface Bandwidth
    266 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 133
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 125 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
  • Technology
    HYPERFLASH
Recommended
OPN
S26KS128SDGBHM030
Product Status active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 1690
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 1690
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S26KS128SDGBHM030 is a 128 Mb automotive-grade HYPERFLASH™ memory built on 65 nm MIRRORBIT™ technology. Supporting HYPERBUS™ at 1.8 V and 3.0 V, it delivers up to 166 MHz clock rate (333 MBps) with DDR center-aligned read strobe. Operating from -40°C to +125°C (AEC-Q100 Grade 1), it offers 100,000 program/erase cycles, 20-year retention, ECC and CRC for data integrity, and advanced sector protection. Typical standby current is 25 µA.

Features

  • 8-bit data bus
  • HYPERBUS™ interface
  • Up to 333 MBps sustained read throughput
  • DDR: two data transfers per clock
  • 166 MHz clock rate at 1.8 V
  • 100 MHz clock rate at 3.0 V
  • 96 ns initial random read access time
  • Configurable burst lengths: 16/32/64 bytes
  • Low power modes: standby 25 µA, deep
  • ECC: 1-bit correction, 2-bit detection
  • Hardware CRC calculation
  • Secure silicon region (1024-byte OTP)

Benefits

  • Fast data access for high-performance systems
  • Flexible interface supports diverse designs
  • High-speed DDR improves throughput
  • Multiple burst lengths optimize transfers
  • Low power modes extend battery life
  • ECC ensures data integrity
  • CRC detects transmission errors
  • Secure region enables device authentication
  • Quick random access reduces latency
  • 8-bit bus simplifies integration
  • Configurable output drive for signal tuning
  • Reliable operation in harsh environments

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{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }