Active and preferred
RoHS Compliant
Lead-free

S25FS512SDSBHB213

ea.
in stock

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S25FS512SDSBHB213
S25FS512SDSBHB213
ea.

Product details

  • Classification
    ISO 26262-ready
  • Density
    512 MBit
  • Family
    FS-S
  • Interface Bandwidth
    80 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    133 / 80
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 105 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive
OPN
S25FS512SDSBHB213
Product Status active and preferred
Infineon Package
Package Name FBGA-24 (002-15534)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
ea. in stock

Product Status
Active
Infineon Package
Package Name FBGA-24 (002-15534)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The S25FS512SDSBHB213 is a 512 Mb automotive-grade SPI NOR flash memory with 65-nm MIRRORBIT™ technology and Eclipse architecture for fast program and erase. Supporting single, dual, quad, and DDR SPI modes, it achieves up to 80 MB/s read rates at 1.7 V to 2.0 V supply. Features include a 512-byte page programming buffer, robust ECC, hybrid and uniform sector erase, AEC-Q100 Grade 2 (-40°C to +105°C), and 20-year data retention. Ideal for automotive embedded code storage.

Features

  • SPI with multi-I/O support
  • DDR and SDR clocking options
  • 24- or 32-bit addressing
  • Compatible with S25FL SPI families
  • Multiple read modes: Normal, Fast, Dual
  • Burst wrap and XIP support
  • 256/512-byte page programming buffer
  • Program and erase suspend/resume
  • Internal ECC with single bit correction
  • Hybrid and uniform sector erase options
  • 100,000 program-erase cycles min
  • 20 year data retention min

Benefits

  • Flexible interface for diverse host
  • High-speed data transfer and boot performance
  • Supports large address spaces for modern
  • Easy migration from legacy SPI designs
  • Optimized for fast and efficient data access
  • Enables execute-in-place (XIP) applications
  • Efficient programming for fast updates
  • Minimized downtime during program/erase
  • Enhanced data reliability and integrity
  • Flexible memory management for varied needs
  • Long device lifetime for demanding use
  • Reliable data storage for mission-critical

Applications

Documents

Design resources

Developer community

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