Active and preferred
RoHS Compliant

IQE030N06NM5SC

OptiMOS™ low-voltage power MOSFET 60 V in PQFN 3.3x3.3 Source-Down DSC package with industry leading RDS(on) and superior thermal performance
Data Sheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

IQE030N06NM5SC
IQE030N06NM5SC
ea.
Data Sheet

Product details

  • Budgetary Price €/1k
    1
  • ID (@25°C) max
    132 A
  • ID max
    132 A
  • IDpuls max
    528 A
  • Operating Temperature
    -55 °C to 175 °C
  • Package
    PQFN 3.3x3.3 Source-Down
  • Polarity
    N
  • Ptot max
    100 W
  • QG (typ @10V)
    39 nC
  • QG
    39 nC
  • RDS (on) (@10V) max
    3 mΩ
  • RDS (on) max
    3 mΩ
  • Special Features
    Dual-Side Cooling
  • VDS max
    60 V
  • VGS(th)
    2.8 V
Recommended
OPN
IQE030N06NM5SCATMA1
Product Status active and preferred
Infineon Package
PG-WHSON-8
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-WHSON-8
Package Name PQFN 3.3x3.3 Source-Down DSC
Packing Size 6000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
OptiMOS™5 60 V PQFN 3.3x3.3 Source-Down: offering a flipped silicon die, which is positioned upside down inside of the components. This adjustment allows the source potential (instead of the drain potential) to be connected to the PCB over the thermal pad. Therefore, it offers several advantages, such as increased thermal capability, advanced power density or improved layout possibilities.

Features

  • Major reduction in RDS(on)30%
  • RthJCover current PQFN
  • Standard & Center Gate available
  • New, optimized layout possibilities

Benefits

  • Enabling highest power density
  • Superior thermal performance
  • Efficient layout for space use
  • Simplified MOSFET parallelization
  • Improved PCB losses
  • Reduced parasitics

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }