Active and preferred
RoHS Compliant

CY8CPLC20-48LTXIT

Data Sheet
package

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CY8CPLC20-48LTXIT
CY8CPLC20-48LTXIT
Data Sheet

Product details

  • Analog Blocks (Programmable)
    12
  • Baud Rate max
    2400 Bit/s
  • CPU
    M8C
  • Development Software
    Y
  • Family
    Powerline Communications
  • Flash
    32 kByte
  • Frequency max
    24 MHz
  • GPIOs
    44
  • I/O Pins
    44
  • I2C
    Programmable
  • Launch Date
    Sep 2009
  • Lead Ball Finish
    Ni/Pd/Au
  • Longevity - 15 years
    Yes
  • Longevity - 20 years
    N/A
  • Longevity - Extended
    Yes
  • Operating Temperature
    -40 °C to 85 °C
  • Operating Voltage
    4.75 V to 5.25 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    Dec 2035
  • PLC Type
    Programmable
  • Publish in NPSG
    Y
  • Publish in PSG
    Y
  • SPI
    Programmable
  • SRAM
    2408 Byte
  • UART
    Programmable
  • Universal Digital Blocks (Programmable)
    16
Recommended
OPN
CY8CPLC20-48LTXIT
Product Status active and preferred
Infineon Package
PG-VQFN-48
Package Name QFN-48 (001-13191)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-VQFN-48
Package Name QFN-48 (001-13191)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY8CPLC20 is an integrated powerline communication (PLC) chip with the powerline modem PHY and network protocol stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers a PSOC™ core that enables system designers to integrate multiple functions on the same chip.

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Documents

Design resources

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