CY7C1512KV18-250BZI
Active and preferred

CY7C1512KV18-250BZI

Data Sheet
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CY7C1512KV18-250BZI
CY7C1512KV18-250BZI
Data Sheet

Product details

  • Density
    72 MBit
  • Family
    QDR-II
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4M x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
Recommended
OPN
CY7C1512KV18-250BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 136
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 136
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1512KV18-250BZI is a 72-Mbit QDR II synchronous pipelined SRAM (4M × 18) with separate read and write data ports for concurrent transactions and no bus turnarounds. It supports two-word burst and DDR interfaces on both ports, operating up to 250 MHz. Core supply is 1.8 V (1.7–1.9 V) with 1.4 V to VDD I/O supply and VREF typ 0.75 V. It is offered in a 165-ball FBGA and specified for industrial range.

Features

  • 72-Mbit QDR II SRAM architecture
  • Separate read/write data ports
  • Concurrent read and write transactions
  • Two-word burst on all accesses
  • DDR I/O, 350 MHz (700 MHz data)
  • 1.5-cycle read latency (DOFF=HIGH)
  • 1-cycle read latency (DOFF=LOW)
  • Input clocks K/K and output C/C
  • Echo clocks CQ/CQ for data capture
  • Core VDD 1.7-1.9 V (nom 1.8 V)
  • VDDQ 1.4 V to VDD, VREF range
  • JTAG IEEE 1149.1 boundary scan

Benefits

  • High bandwidth for fast networking
  • No bus turnaround delays
  • Parallel R/W boosts throughput
  • Two-word bursts cut command load
  • DDR at 700 MHz speeds transfers
  • Low-latency reads for tight timing
  • DOFF selects latency vs pipeline
  • Separate clocks ease timing closure
  • Echo clocks simplify PCB capture
  • 1.8 V core helps reduce power
  • HSTL levels fit high-speed links
  • JTAG speeds board test and debug

Applications

Documents

Design resources

Partner solutions

Developer community

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