CY7C1472BV33-167AXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1472BV33-167AXI

Datasheet
package

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CY7C1472BV33-167AXI
CY7C1472BV33-167AXI
Datasheet

Product details

  • Architecture
    NoBL, Pipeline
  • Bank Switching
    N
  • Data Width
    x 18
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    167 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    4Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1472BV33-167AXI
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1472BV33-167AXI is a 72-Mbit (4M × 18) synchronous pipelined burst SRAM with NoBL architecture for zero-wait-state read/write transitions. It runs from a 3.3 V core supply with 3.3 V/2.5 V I/O and supports 167 MHz bus operation. Fully registered inputs/outputs enable 4-word linear or interleaved bursts, with byte-write via BWa/BWb, CEN clock gating, ZZ sleep mode, and IEEE 1149.1 JTAG boundary scan.

Features

  • 72-Mbit sync pipelined SRAM
  • No Bus Latency (NoBL) logic
  • 250 MHz bus ops, zero wait states
  • Registered inputs and outputs
  • Linear or interleaved burst order
  • Byte write with BWx byte selects
  • VDD 3.135 V to 3.6 V single rail
  • VDDQ I/O: 2.5 V or 3.3 V
  • 3.0 ns clock-to-output (250 MHz)
  • ZZ sleep mode and Stop Clock
  • IEEE 1149.1 JTAG boundary scan
  • Neutron SER: 361 FIT/Mb typ, 25C

Benefits

  • Run back-to-back ops with no stalls
  • More throughput each clock cycle
  • Drop-in path for ZBT designs
  • Predictable timing simplifies closure
  • Burst support fits streaming data
  • Byte writes cut rewrite bandwidth
  • Single-rail core eases power design
  • Direct 2.5/3.3 V logic connection
  • 3.0 ns tCO reduces read latency
  • Sleep/stop clock cuts idle power
  • JTAG simplifies board test & debug
  • Lower soft-error risk in systems

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