Please note that this is an end of life product. See newer alternative product version Please note that this is an end of life product. See newer alternative product version
CY25560SXC
END OF LIFE
discontinued
RoHS Compliant

CY25560SXC

END OF LIFE
Datasheet
package

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CY25560SXC
CY25560SXC
Datasheet


Product details

  • Core/IO Operating Voltages ((V))
    3.3
  • Features
    1-Output Programmable Spread Spectrum Clock Generator
  • I/O Voltage ((V))
    3.3
  • Input Frequency range
    25 MHz to 100 MHz
  • Input Type
    Xtal/Ref-in CMOS
  • Lead Ball Finish
    Ni/Pd/Au
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    2.97 V to 3.6 V
  • Output Frequency range
    25 MHz to 100 MHz
  • Output Signal Type
    CMOS
  • Outputs
    1
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Commercial
  • Spread Spectrum
    Y

OPN
CY25560SXC
Product Status discontinued
Infineon Package
PG-DSO-8
Package Name SOIC-8 (51-85066 )
Packing Size 970
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes

Product Status discontinued
Infineon Package
PG-DSO-8
Package Name SOIC-8 (51-85066 )
Packing Size 970
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY25560SXC is a 1-output programmable spread spectrum clock generator for EMI reduction in high-speed digital systems. It operates from 2.97 to 3.6 V with 25 to 100 MHz input and output frequency, supports crystal and CMOS inputs, and integrates a single PLL. The device offers selectable spread percentages, CMOS output, and is housed in an 8-pin SOIC with Ni/Pd/Au lead finish. RoHS compliant, commercial grade (0 to 70°C).

Features

  • Spread spectrum clock generation
  • 25–100 MHz input frequency range
  • Nine selectable spread options
  • Accepts clock and crystal inputs
  • Center spread modulation
  • Low cycle-to-cycle jitter
  • Frequency spread disable function
  • Tri-level logic for flexible control
  • PLL-based architecture
  • Internal resistor dividers for logic

Benefits

  • Reduces EMI by 8–16 dB
  • Flexible EMI reduction for compliance
  • Suits wide range of applications
  • Easy integration with clock/crystal
  • Flexible spread selection for design
  • Low jitter ensures signal integrity
  • Simple logic control saves pins
  • PLL design delivers stable output
  • No external resistors for logic setup
  • Disable spread for test/debug

Applications

Documents

Design resources

Partner solutions

Developer community