CY23EP05SXC-1H
Active
RoHS Compliant

CY23EP05SXC-1H

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CY23EP05SXC-1H
CY23EP05SXC-1H

Product details

  • Category
    Zero Delay Buffers
  • Core/IO Operating Voltages ((V))
    2.5/3.3
  • Features
    2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output Zero Delay Buffer
  • Function
    See datasheet
  • I/O Voltage ((V))
    2.5/3.3
  • Input Frequency range
    10 MHz to 220 MHz
  • Input Type
    LVCMOS/LVTTL
  • Lead Ball Finish
    Pure Sn
  • On-chip Clock Generation (PLL)
    1
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    2.3 V to 3.6 V
  • Output Frequency range
    10 MHz to 220 MHz
  • Output Signal Type
    LVCMOS
  • Outputs
    5
  • Peak Reflow Temp
    260 °C
  • Publish in NPSG
    N
  • Publish in PSG
    Y
  • Qualification
    Commercial
  • Spread Spectrum
    N
Recommended
OPN
CY23EP05SXC-1H
Product Status active
Infineon Package
PG-DSO-8
Package Name SOIC-8 (51-85066 )
Packing Size 970
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-DSO-8
Package Name SOIC-8 (51-85066 )
Packing Size 970
Packing Type TUBE
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY23EP05SXC-1 H is a high-drive zero delay buffer with five LVCMOS outputs, supporting 10 to 220 MHz input and output frequencies and operating from a 2.3 to 3.6 V supply. It features on-chip PLL clock generation, low jitter, and zero input-output propagation delay. Designed for commercial temperature range (0 to 70°C), it is RoHS compliant and housed in an 8-pin SOIC package, ideal for clock distribution in high-speed digital systems.

Features

  • Zero input-output propagation delay
  • Five low-skew clock outputs
  • On-chip PLL for clock synchronization
  • 22 ps typical cycle-to-cycle jitter
  • 13 ps typical period jitter
  • 10–220 MHz operating frequency
  • High and standard drive strength options
  • Power-down mode under 25 μA
  • Output-output skew as low as 30 ps
  • Rise/fall time down to 0.5 ns
  • Input duty cycle 25–75%
  • Output duty cycle 45–55%

Benefits

  • Eliminates timing delays in clock trees
  • Drives multiple loads with minimal skew
  • Maintains clock integrity and alignment
  • Ultra-low jitter for precise timing
  • Stable clock period for sensitive
  • Supports wide range of applications
  • Flexible drive for various load
  • Saves power in standby operation
  • Ensures precise multi-output timing
  • Fast signal transitions for high-speed
  • Accepts varied input clock shapes
  • Consistent output for reliable design

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