Active and preferred
RoHS Compliant
Lead-free

CY15V104QN-50BFXI

Data Sheet
package

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CY15V104QN-50BFXI
CY15V104QN-50BFXI
Data Sheet

Product details

  • Density
    4 MBit
  • Family
    Excelon
  • Frequency
    50 MHz
  • Interfaces
    SPI
  • Lead Ball Finish
    Ni/Au
  • Operating Temperature
    -40 °C to 85 °C
  • Operating Voltage
    1.71 V to 1.89 V
  • Organization (X x Y)
    512Kb x 8
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
Recommended
OPN
CY15V104QN50BFXIXQLA1
Product Status active and preferred
Infineon Package
PG-UFLGA-8
Package Name LGA-8 (002-34146)
Packing Size 4900
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-UFLGA-8
Package Name LGA-8 (002-34146)
Packing Size 4900
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CY15V104QN-50BFXI is a 4-Mb EXCELON™ LP ferroelectric RAM (F-RAM) with 512K × 8 organization, accessed via an SPI interface supporting up to 50 MHz. It delivers 10^15 read/write cycle endurance, 151-year data retention at 60°C, and instant non-volatile writes with zero delay. Operating from 1.71 V to 1.89 V over –40°C to +85°C, it features low active current and advanced write protection.

Features

  • 4-Mb ferroelectric RAM, 512K × 8 organization
  • Virtually unlimited 10^15 read/write cycles
  • 151-year data retention at 70°C
  • SPI interface up to 50 MHz
  • Supports SPI mode 0 and mode 3
  • Hardware and software write protection
  • Dedicated 256-byte special sector
  • Unique device ID and serial number
  • Low active current: 2.4 mA at 40 MHz
  • Standby current: 2.3 µA (typ)
  • Deep power-down: 0.7 µA (typ)
  • Hibernate mode: 0.1 µA (typ)

Benefits

  • Reliable for frequent, rapid data logging
  • No wear-out, ideal for mission-critical use
  • Long-term data integrity, minimal refresh
  • Fast SPI enables high-speed system design
  • Flexible integration with standard SPI hosts
  • Enhanced data security and tamper resistance
  • Special sector survives soldering reflow
  • Easy device tracking and authentication
  • Low power extends battery/system life
  • Minimizes standby energy consumption
  • Deep sleep reduces power in idle states
  • Hibernate mode for ultra-low power standby

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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