AURIX™ TC4x - 32-bit TriCore™

Infineon's AURIX™ TC4x family of 32-bit TriCore™ microcontrollers for automotive E/E, ADAS, eMobility, and AI applications.

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About

TC4x sub-families: TC4Dx, TC45x, TC48x, TC49x

The AURIX™ TC4x is Infineon's next-generation family of 32-bit TriCore™ microcontrollers designed for automotive E/E architectures, ADAS, eMobility, and AI applications. The TC4x family provides an upward migration path from the AURIX™ TC3x family of ASIL-compliant automotive MCUs.

The TC4x portfolio is organized into four sub-families: AURIX™ TC4Dx, AURIX™ TC45x, AURIX™ TC48x, and AURIX™ TC49x. Each sub-family targets a distinct tier of automotive compute demand, from domain and zone control to advanced sensor fusion and AI inference.

The TC4x family delivers up to 6 TriCore™ v1.8 cores at up to 500 MHz, up to 25 MBits of on-chip flash with SOTA update support, dual 5 GBit Ethernet ports, dual PCIe 3.0 lanes, and CAN-XL connectivity across its sub-families.

Design advantages for automotive E/E and ADAS systems

  • TC3x migration with software reuse: Migrating to a next-generation MCU requires re-qualification effort. The TC4x common software architecture supports reuse of existing AURIX™ TC3x algorithms, reducing OEM and Tier 1 re-qualification effort and software costs.
  • Scalable AI and parallel processing: The Parallel Processing Unit (PPU) enables advanced ADAS and autonomous driving functions within TC4x without a separate AI accelerator, reducing system BOM complexity and integration risk.
  • ISO 21434 compliant cybersecurity: The integrated CSRM/CSS accelerator provides hardware-enforced cybersecurity, meeting ISO 21434 requirements without relying on software-only security layers.
  • High-speed connectivity for E/E architectures: Native support for 5G-bit Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet provides necessary flexibility for zonal and domain E/E architectures.
  • Common power supply design across the TC4x portfolio: Designing power supply circuits for multiple MCU variants increases qualification effort and BOM complexity. The TLF4x OPTIREG™ PMIC is scalable across TC4x sub-families, so a single power supply design covers multiple variants.

CPU cores, clock speed, memory, and connectivity ranges

  • CPU Core Count and Architecture: TC4x integrates up to 6 TriCore™ v1.8 cores at up to 500 MHz in lockstep. Lockstep is required for ASIL-D compliance. Higher core counts enable parallel task execution for domain controllers managing vehicle functions.
  • On-Chip Non-Volatile Memory (NVM): On-chip NVM provides up to 25 MBits of flash with SOTA support. Larger on-chip NVM reduces external flash dependence and simplifies SOTA partition management.
  • Connectivity Interfaces: TC4x supports dual 5GBit Ethernet ports (including bridge), dual PCIe 3.0 lanes at 8GBit/s, four 10/100MBit Ethernet ports with 10BASE-T1S support, and CAN-XL. Higher connectivity bandwidth determines whether the MCU can support zonal E/E architectures without an external network switch.
  • Functional Safety Level: ASIL-D, as defined by ISO 26262, is the highest automotive safety level, requiring hardware redundancy and diagnostic coverage above 99%. A higher ASIL rating influences sub-family selection and system architecture. The TC4x PPU subsystem is rated to ASIL-D. 

Processing, accelerator, and qualification performance

  • Processing performance: The TC4x’s TriCore 1.8 architecture delivers up to 5.07 CoreMark/MHz per core at up to 500 MHz
  • AI and radar acceleration: The PPU delivers up to 48 GOPS of parallel-processing performance for AI inference and signal-processing workloads, with safety support up to ASIL-D. The DRE handles data routing, while the SPU3 provides dedicated on-chip radar signal processing.
  • Cybersecurity: The CSRM/CSS hardware accelerator provides hardware-enforced security compliant with ISO 21434.
  • Audio processing:The TC4x family supports 8-to-1 PCM mixing, PLL-based audio clock generation, TSN media-clock synchronization, and I2S/TDM interfaces. This can allow in-cabin designs incorporating noise cancellation, AVAS, and audio-zone management to avoid a discrete audio DSP, depending on the implementation.
  • Qualification Standard — Result
    • ISO 26262: ASIL-D (PPU subsystem)
    • ISO 21434: CSRM/CSS compliant
    • AEC-Q100: Qualified to Grade 1 and supports an ambient operating temperature range of −40°C to +125°C

Domain control, ADAS, eMobility, and in-cabin systems

  • Domain and zone controllers: For next-generation domain and zone controller architectures requiring 5G-bit Ethernet, PCIe, and multi-core real-time processing, the TC4x is recommended because its sub-family structure reduces distinct ECU hardware variants a Tier 1 must qualify.
  • ADAS and autonomous driving: ADAS is the primary application for TC48x. For sensor fusion and AI inference, the TC4x PPU provides ASIL-D-rated parallel processing without a separate AI accelerator. The integrated SPU is recommended for radar front-end designs requiring on-chip radar signal processing.
  • eMobility and powertrain control: The TC45x is recommended for xEV integration platforms and high-end engine management. The TC49x is recommended for inverter control, DC-DC conversion, OBC, and battery management.
  • In-cabin audio and infotainment: For in-cabin noise canceling, AVAS, and audio zone management, the TC4x integrated audio subsystem is recommended because it eliminates the need for a dedicated audio DSP, reducing BOM cost and PCB area. 

Five-step selection framework for TC4x sub-families

Step 1: Define the E/E architecture tier

Select TC48x for ADAS applications and TC4Dx for zone control, or TC45x for 77GHz radar processing. If you require xEV powertrain or engine management, select TC49x.

Step 2: Confirm functional safety level

If your application requires ASIL-D with AI or sensor fusion, select a sub-family with the PPU. TC4x sub-families without the PPU aren’t recommended for ASIL-D AI applications.

Step 3: Assess AI and processing requirements

If your design includes neural network inference, radar processing, or advanced audio, confirm PPU and SPU availability in the selected sub-family.

Step 4: Evaluate TC3x migration effort

If migrating from TC3x, assess software reuse potential using AURIX™ DRIVECORE and the Synopsys MetaWare toolkit.

Step 5: Confirm power supply compatibility

Verify the TLF4x OPTIREG™ PMIC covers the selected sub-family's power rail requirements.

 

TriCore™ v1.8, AURIX™ Accelerator Suite, and DRIVECORE

  • TriCore™ v1.8 processor architecture: TC4x is built on the TriCore™ v1.8 core, providing an upward-compatible instruction set from the TC3x generation. TriCore™ combines a RISC CPU, DSP, and microcontroller in a single core, reducing context-switch overhead for mixed real-time and signal processing workloads.
  • AURIX™ Accelerator Suite for automotive AI and safety: The AURIX™ Accelerator Suite integrates the PPU (AI inference, ASIL-D), DRE (data routing), SPU (radar), and CSRM/CSS (cybersecurity) on a single device, reducing discrete processing components in domain controller designs. This integration eliminates the need for separate AI, radar, and security co-processors, reducing board area and system BOM.
  • AURIX™ DRIVECORE software bundle: AURIX™ DRIVECORE includes Infineon MCAL drivers, AUTOSAR Complex Device Drivers, and toolchain integration components including the Synopsys MetaWare toolkit and the Synopsys Virtualizer Development Kit (VDK). DRIVECORE reduces TC3x migration effort and simplifies supplier management by consolidating software assets under a single commercial agreement.
DRIVECORE™ for AURIX™

Access documentation, training, and expert design-in support

The AURIX™ TC4x design-in ecosystem includes the Synopsys MetaWare toolkit, HSP for MathWorks Simulink®, the Synopsys Virtualizer Development Kit (VDK), and Infineon MCAL drivers and AUTOSAR Complex Device Drivers via AURIX™ DRIVECORE.

Digital Collaterals: Datasheets, user manuals, code examples, and presentations in one HTML-integrated resource, accessible across any device.

Discover AURIX™ digital collaterals

Additional Documentation: Register on the myInfineon (myICP) for technical add-on documentation, training, and tools. Send your access request to AURIX@infineon.com with your company email. myICP

myICP
How to register

Training: Expert tutorials and hands-on guides for AURIX™ Development Studio, for beginners and experienced engineers alike. Microcontroller Training and Video Hub

Preferred Design Houses: Infineon's network of AURIX™-trained partners provides product and application-specific support, on-site consulting, and dedicated automotive security expertise. 

Microcontroller Training and Video Hub
AURIX™ Preferred Design Houses

TC4x sub-families: TC4Dx, TC45x, TC48x, TC49x

The AURIX™ TC4x is Infineon's next-generation family of 32-bit TriCore™ microcontrollers designed for automotive E/E architectures, ADAS, eMobility, and AI applications. The TC4x family provides an upward migration path from the AURIX™ TC3x family of ASIL-compliant automotive MCUs.

The TC4x portfolio is organized into four sub-families: AURIX™ TC4Dx, AURIX™ TC45x, AURIX™ TC48x, and AURIX™ TC49x. Each sub-family targets a distinct tier of automotive compute demand, from domain and zone control to advanced sensor fusion and AI inference.

The TC4x family delivers up to 6 TriCore™ v1.8 cores at up to 500 MHz, up to 25 MBits of on-chip flash with SOTA update support, dual 5 GBit Ethernet ports, dual PCIe 3.0 lanes, and CAN-XL connectivity across its sub-families.

Design advantages for automotive E/E and ADAS systems

  • TC3x migration with software reuse: Migrating to a next-generation MCU requires re-qualification effort. The TC4x common software architecture supports reuse of existing AURIX™ TC3x algorithms, reducing OEM and Tier 1 re-qualification effort and software costs.
  • Scalable AI and parallel processing: The Parallel Processing Unit (PPU) enables advanced ADAS and autonomous driving functions within TC4x without a separate AI accelerator, reducing system BOM complexity and integration risk.
  • ISO 21434 compliant cybersecurity: The integrated CSRM/CSS accelerator provides hardware-enforced cybersecurity, meeting ISO 21434 requirements without relying on software-only security layers.
  • High-speed connectivity for E/E architectures: Native support for 5G-bit Ethernet, PCIe, CAN-XL, and 10BASE-T1S Ethernet provides necessary flexibility for zonal and domain E/E architectures.
  • Common power supply design across the TC4x portfolio: Designing power supply circuits for multiple MCU variants increases qualification effort and BOM complexity. The TLF4x OPTIREG™ PMIC is scalable across TC4x sub-families, so a single power supply design covers multiple variants.

CPU cores, clock speed, memory, and connectivity ranges

  • CPU Core Count and Architecture: TC4x integrates up to 6 TriCore™ v1.8 cores at up to 500 MHz in lockstep. Lockstep is required for ASIL-D compliance. Higher core counts enable parallel task execution for domain controllers managing vehicle functions.
  • On-Chip Non-Volatile Memory (NVM): On-chip NVM provides up to 25 MBits of flash with SOTA support. Larger on-chip NVM reduces external flash dependence and simplifies SOTA partition management.
  • Connectivity Interfaces: TC4x supports dual 5GBit Ethernet ports (including bridge), dual PCIe 3.0 lanes at 8GBit/s, four 10/100MBit Ethernet ports with 10BASE-T1S support, and CAN-XL. Higher connectivity bandwidth determines whether the MCU can support zonal E/E architectures without an external network switch.
  • Functional Safety Level: ASIL-D, as defined by ISO 26262, is the highest automotive safety level, requiring hardware redundancy and diagnostic coverage above 99%. A higher ASIL rating influences sub-family selection and system architecture. The TC4x PPU subsystem is rated to ASIL-D. 

Processing, accelerator, and qualification performance

  • Processing performance: The TC4x’s TriCore 1.8 architecture delivers up to 5.07 CoreMark/MHz per core at up to 500 MHz
  • AI and radar acceleration: The PPU delivers up to 48 GOPS of parallel-processing performance for AI inference and signal-processing workloads, with safety support up to ASIL-D. The DRE handles data routing, while the SPU3 provides dedicated on-chip radar signal processing.
  • Cybersecurity: The CSRM/CSS hardware accelerator provides hardware-enforced security compliant with ISO 21434.
  • Audio processing:The TC4x family supports 8-to-1 PCM mixing, PLL-based audio clock generation, TSN media-clock synchronization, and I2S/TDM interfaces. This can allow in-cabin designs incorporating noise cancellation, AVAS, and audio-zone management to avoid a discrete audio DSP, depending on the implementation.
  • Qualification Standard — Result
    • ISO 26262: ASIL-D (PPU subsystem)
    • ISO 21434: CSRM/CSS compliant
    • AEC-Q100: Qualified to Grade 1 and supports an ambient operating temperature range of −40°C to +125°C

Domain control, ADAS, eMobility, and in-cabin systems

  • Domain and zone controllers: For next-generation domain and zone controller architectures requiring 5G-bit Ethernet, PCIe, and multi-core real-time processing, the TC4x is recommended because its sub-family structure reduces distinct ECU hardware variants a Tier 1 must qualify.
  • ADAS and autonomous driving: ADAS is the primary application for TC48x. For sensor fusion and AI inference, the TC4x PPU provides ASIL-D-rated parallel processing without a separate AI accelerator. The integrated SPU is recommended for radar front-end designs requiring on-chip radar signal processing.
  • eMobility and powertrain control: The TC45x is recommended for xEV integration platforms and high-end engine management. The TC49x is recommended for inverter control, DC-DC conversion, OBC, and battery management.
  • In-cabin audio and infotainment: For in-cabin noise canceling, AVAS, and audio zone management, the TC4x integrated audio subsystem is recommended because it eliminates the need for a dedicated audio DSP, reducing BOM cost and PCB area. 

Five-step selection framework for TC4x sub-families

Step 1: Define the E/E architecture tier

Select TC48x for ADAS applications and TC4Dx for zone control, or TC45x for 77GHz radar processing. If you require xEV powertrain or engine management, select TC49x.

Step 2: Confirm functional safety level

If your application requires ASIL-D with AI or sensor fusion, select a sub-family with the PPU. TC4x sub-families without the PPU aren’t recommended for ASIL-D AI applications.

Step 3: Assess AI and processing requirements

If your design includes neural network inference, radar processing, or advanced audio, confirm PPU and SPU availability in the selected sub-family.

Step 4: Evaluate TC3x migration effort

If migrating from TC3x, assess software reuse potential using AURIX™ DRIVECORE and the Synopsys MetaWare toolkit.

Step 5: Confirm power supply compatibility

Verify the TLF4x OPTIREG™ PMIC covers the selected sub-family's power rail requirements.

 

TriCore™ v1.8, AURIX™ Accelerator Suite, and DRIVECORE

  • TriCore™ v1.8 processor architecture: TC4x is built on the TriCore™ v1.8 core, providing an upward-compatible instruction set from the TC3x generation. TriCore™ combines a RISC CPU, DSP, and microcontroller in a single core, reducing context-switch overhead for mixed real-time and signal processing workloads.
  • AURIX™ Accelerator Suite for automotive AI and safety: The AURIX™ Accelerator Suite integrates the PPU (AI inference, ASIL-D), DRE (data routing), SPU (radar), and CSRM/CSS (cybersecurity) on a single device, reducing discrete processing components in domain controller designs. This integration eliminates the need for separate AI, radar, and security co-processors, reducing board area and system BOM.
  • AURIX™ DRIVECORE software bundle: AURIX™ DRIVECORE includes Infineon MCAL drivers, AUTOSAR Complex Device Drivers, and toolchain integration components including the Synopsys MetaWare toolkit and the Synopsys Virtualizer Development Kit (VDK). DRIVECORE reduces TC3x migration effort and simplifies supplier management by consolidating software assets under a single commercial agreement.
DRIVECORE™ for AURIX™

Access documentation, training, and expert design-in support

The AURIX™ TC4x design-in ecosystem includes the Synopsys MetaWare toolkit, HSP for MathWorks Simulink®, the Synopsys Virtualizer Development Kit (VDK), and Infineon MCAL drivers and AUTOSAR Complex Device Drivers via AURIX™ DRIVECORE.

Digital Collaterals: Datasheets, user manuals, code examples, and presentations in one HTML-integrated resource, accessible across any device.

Discover AURIX™ digital collaterals

Additional Documentation: Register on the myInfineon (myICP) for technical add-on documentation, training, and tools. Send your access request to AURIX@infineon.com with your company email. myICP

myICP
How to register

Training: Expert tutorials and hands-on guides for AURIX™ Development Studio, for beginners and experienced engineers alike. Microcontroller Training and Video Hub

Preferred Design Houses: Infineon's network of AURIX™-trained partners provides product and application-specific support, on-site consulting, and dedicated automotive security expertise. 

Microcontroller Training and Video Hub
AURIX™ Preferred Design Houses
Documents