AURIX™ TC3x - 32-bit TriCore™

Multi-core TriCore™ MCUs with integrated HSM security and ISO 26262 ASIL-D support for automotive and industrial embedded control.

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About

TC3x sub-families: TC32x to TC39x series

The AURIX™ TC3x is a family of 32-bit microcontrollers built on the TriCore™ architecture, designed for safety-critical automotive and industrial embedded control applications. Infineon's AURIX™ TC3x portfolio spans the TC32xLP low-power series to the TC39xXA high-performance series, covering 1 to 6 TriCore™ cores, clock frequencies up to 400 MHz, flash memory up to 16 MB, and on-chip RAM exceeding 6 MB. Discover the full AURIX™ TC3x portfolio.

Sub-families are organized by core count and application scope: the TC32xLP and TC33x series address single- and dual-core embedded control; the TC35xTA and TC36xDP series cover mid-range powertrain and ADAS applications; and the TC37x, TC38xQP, and TC39x series address high-core-count domain control and data fusion at up to 400 MHz.

All TC3x devices share a TriCore™ Instruction Set Architecture (ISA) and a scalable peripheral set, including CAN FD, LIN, Gigabit Ethernet, Signal Processing Units (SPU), and an eMMC interface for external flash.

AURIX™ TC3x portfolio
AURIX™ TC3x AI-capable products

Key benefits: ASIL-D, HSM security, multi-core, and radar processing

  • ASIL-D functional safety architecture: The AURIX™ TC3x implements a lockstep CPU architecture and hardware safety mechanisms supporting ISO 26262 ASIL-D compliance, reducing the need for external safety monitors in domain control designs and system BOM complexity.
  • Integrated Hardware Security Module (HSM): The TC3x integrates HSM with asymmetric cryptography accelerators and Full EVITA, enabling secure boot and in-vehicle network authentication without an external security co-processor.
  • Scalable multi-core architecture for real-time workload partitioning: The TC3x supports parallel execution of real-time control and sensor processing across multiple TriCore™ cores, allowing engineers to partition safety and non-safety workloads without additional external processors.
  • Radar signal processing via dedicated SPUs: On-chip SPUs accelerate radar data processing for ADAS, reducing the need for a discrete radar DSP and lowering system power.
  • Scalable pinout and feature set across sub-families: The TC3x offers scalable pinouts and feature sets, allowing software and PCB layouts to be reused across variants.

CPU core count and clock frequency: 1 to 6 cores, up to 400 MHz

  • CPU core count: CPU core count determines how many real-time tasks a microcontroller can execute concurrently. The AURIX™ TC3x spans 1 to 6 TriCore™ cores.
  • CPU clock frequency: CPU clock frequency sets the upper bound on instruction throughput for time-critical control loops. Clock frequency ranges to 300 MHz across most sub-families, and up to 400 MHz on the TC38xQP and TC39xXX series.
  • Flash memory: Flash memory determines how much application code, calibration data, and bootloader firmware the device stores without external memory. On-chip flash ranges up to 16 MB.
  • Integrated RAM: Integrated RAM determines real-time data volume, stack, and communication buffers without external SRAM. On-chip RAM exceeds 6 MB.
  • Functional Safety Level (ASIL): ASIL-D, as defined by ISO 26262, is the highest automotive safety integrity level. A higher ASIL rating requires greater hardware redundancy and diagnostic coverage above 99%, directly influencing sub-family selection and system architecture. 

Functional safety: ASIL-D architecture and ISO 26262 compliance

  • ASIL-D safety architecture: The TC3x safety architecture supports ASIL-D decomposition per ISO 26262, achieving a diagnostic coverage target above 99% through lockstep CPU execution and integrated hardware safety mechanisms. This eliminates the need for external safety monitors, reducing system BOM and board area.
  • HSM security performance: asymmetric cryptography and full EVITA: The integrated HSM supports asymmetric cryptography acceleration and Full EVITA, completing secure boot and in-vehicle network authentication without an external security IC.
  • Radar processing: on-chip SPU offload for ADAS applications: The on-chip SPUs offload radar signal processing from the TriCore™ cores, maintaining real-time control loop performance under peak sensor data loads.
  • Qualification: AEC-Q100: The AURIX™ TC3x is qualified to Automotive Electronics Council Q100 (AEC-Q100), confirming suitability for automotive operating environments.
Learn more about functional safety

Domain control, ADAS, powertrain, and connected car

  • Automotive domain control and data fusion: For domain control units consolidating radar, LIDAR, and camera sensor inputs, the TC37x, TC38x, and TC39x sub-families are recommended because their 4 to 6 TriCore™ cores support parallel ASIL-D-compliant processing within a single device.
  • ADAS: radar, LIDAR, and camera processing: The TC33xTA and TC39xXA sub-families include dedicated SPUs and ADAS-specific peripheral configurations for radar front-end processing that eliminate the need for a discrete radar DSP.
  • Powertrain and electrification: The family supports inverter control, battery management, onboard charger, and DC-DC converter applications, meeting the functional safety requirements of ISO 26262 for high-voltage powertrain systems.
  • Connected car: telematics, gateway, and In-Vehicle charging: Integrated connectivity peripherals support telematics units and connected gateways. The integrated HSM with Full EVITA addresses UN R155 cybersecurity compliance requirements, covering secure over-the-air update and in-vehicle network authentication without external security IC.
Learn more about automotive application

How to choose an AURIX™ TC3x sub-family for your design

Step 1: Define core count

For concurrent execution of safety monitoring, motor control, and communication, select TC37x, TC38x, or TC39x (4–6 cores). For single-domain control, choose TC32x or TC33x sub-families.

Step 2: Confirm functional safety level

For ISO 26262 ASIL-D applications (domain control, steering, airbag), select a sub-family with a confirmed ASIL-D safety manual.

Step 3: Size flash and RAM to software footprint

Select a sub-family with at least 20% headroom above the AUTOSAR stack, combined code, calibration data and bootloader estimate.

Step 4: Match connectivity to system topology

Gigabit Ethernet is available on selected sub-families. CAN FD and LIN are available across the TC3x portfolio.

Step 5: Filter by ADAS features if required

For radar processing, select sub-families with integrated SPUs (TC33xTA, TC39xXA). Use the AURIX™ TC3x parametric selection tool:

Parameter: Sub-Family

  • 1-3 cores, single domain: TC32x, TC33x
  • 4-6 cores, ASIL-D: TC37x, TC38x, TC39x
  • Radar SPU : TC33xTA, TC39xXA

TriCore™ architecture, migration, PDH ecosystem, and myICP

  • TriCore™ architecture: unified real-time processing core
    • TriCore™ is a unified 32-bit microcontroller-DSP architecture, combining microcontroller real-time capability, DSP computational throughput, and RISC load-store code density in a reprogrammable core. It supports 16-bit and 32-bit instruction formats, 4 GB of address space, and hardware memory protection. All TC3x sub-families share a common TriCore™ ISA, protecting software investment across the portfolio.
  • Pin compatibility with AURIX™ TC2x for migration continuity
    • The AURIX™ TC3x family is pin-compatible with the AURIX™ TC2x. This allows engineers to reuse PCB layouts and reduce re-qualification effort when migrating from TC2x to TC3x.
  • AURIX™ Preferred Design House (PDH) ecosystem
    • Infineon supports designs through a network of PDHs trained in AURIX™ MCU development. Local field application engineers address standard questions; dedicated automotive security experts handle complex safety topics.
  • myICP collaboration platform for technical documentation
    • Engineers can access additional documentation, training, and tools by registering on myICP.
Learn more about AURIX™ Preferred Design Houses
myICP
How to register

Software, eval kits, and technical documentation for TC3x

  • Software, SDKs & Tools: Infineon provides a free Eclipse-based IDE for TC3x application development, low-level driver libraries for peripheral configuration, and AUTOSAR BSW and MCAL packages.
  • Evaluation kits: Evaluation kits are available to support hardware bring-up and software development for TC3x sub-families. Each kit provides a ready-to-test hardware platform, reducing bring-up time at the start of development.
  • Digital collaterals: Datasheets, user manuals, code examples, and presentations are accessible in HTML format via the AURIX™ digital collaterals portal across desktop and mobile devices.
  • Technical documentation via myICP: Additional documentation, training, and tools are available through the myInfineon Collaboration Platform (myICP). To register, sign up at myInfineon and send an access request to AURIX@infineon.com using a company email address.
  • Microcontroller training and video hub: Expert tutorials and hands-on guides for AURIX™ Development Studio and TC3x peripheral configuration are available through the Microcontroller Training and Video Hub.
Discover AURIX™ digital collaterals
Microcontroller training and video hub

TC3x sub-families: TC32x to TC39x series

The AURIX™ TC3x is a family of 32-bit microcontrollers built on the TriCore™ architecture, designed for safety-critical automotive and industrial embedded control applications. Infineon's AURIX™ TC3x portfolio spans the TC32xLP low-power series to the TC39xXA high-performance series, covering 1 to 6 TriCore™ cores, clock frequencies up to 400 MHz, flash memory up to 16 MB, and on-chip RAM exceeding 6 MB. Discover the full AURIX™ TC3x portfolio.

Sub-families are organized by core count and application scope: the TC32xLP and TC33x series address single- and dual-core embedded control; the TC35xTA and TC36xDP series cover mid-range powertrain and ADAS applications; and the TC37x, TC38xQP, and TC39x series address high-core-count domain control and data fusion at up to 400 MHz.

All TC3x devices share a TriCore™ Instruction Set Architecture (ISA) and a scalable peripheral set, including CAN FD, LIN, Gigabit Ethernet, Signal Processing Units (SPU), and an eMMC interface for external flash.

AURIX™ TC3x portfolio
AURIX™ TC3x AI-capable products

Key benefits: ASIL-D, HSM security, multi-core, and radar processing

  • ASIL-D functional safety architecture: The AURIX™ TC3x implements a lockstep CPU architecture and hardware safety mechanisms supporting ISO 26262 ASIL-D compliance, reducing the need for external safety monitors in domain control designs and system BOM complexity.
  • Integrated Hardware Security Module (HSM): The TC3x integrates HSM with asymmetric cryptography accelerators and Full EVITA, enabling secure boot and in-vehicle network authentication without an external security co-processor.
  • Scalable multi-core architecture for real-time workload partitioning: The TC3x supports parallel execution of real-time control and sensor processing across multiple TriCore™ cores, allowing engineers to partition safety and non-safety workloads without additional external processors.
  • Radar signal processing via dedicated SPUs: On-chip SPUs accelerate radar data processing for ADAS, reducing the need for a discrete radar DSP and lowering system power.
  • Scalable pinout and feature set across sub-families: The TC3x offers scalable pinouts and feature sets, allowing software and PCB layouts to be reused across variants.

CPU core count and clock frequency: 1 to 6 cores, up to 400 MHz

  • CPU core count: CPU core count determines how many real-time tasks a microcontroller can execute concurrently. The AURIX™ TC3x spans 1 to 6 TriCore™ cores.
  • CPU clock frequency: CPU clock frequency sets the upper bound on instruction throughput for time-critical control loops. Clock frequency ranges to 300 MHz across most sub-families, and up to 400 MHz on the TC38xQP and TC39xXX series.
  • Flash memory: Flash memory determines how much application code, calibration data, and bootloader firmware the device stores without external memory. On-chip flash ranges up to 16 MB.
  • Integrated RAM: Integrated RAM determines real-time data volume, stack, and communication buffers without external SRAM. On-chip RAM exceeds 6 MB.
  • Functional Safety Level (ASIL): ASIL-D, as defined by ISO 26262, is the highest automotive safety integrity level. A higher ASIL rating requires greater hardware redundancy and diagnostic coverage above 99%, directly influencing sub-family selection and system architecture. 

Functional safety: ASIL-D architecture and ISO 26262 compliance

  • ASIL-D safety architecture: The TC3x safety architecture supports ASIL-D decomposition per ISO 26262, achieving a diagnostic coverage target above 99% through lockstep CPU execution and integrated hardware safety mechanisms. This eliminates the need for external safety monitors, reducing system BOM and board area.
  • HSM security performance: asymmetric cryptography and full EVITA: The integrated HSM supports asymmetric cryptography acceleration and Full EVITA, completing secure boot and in-vehicle network authentication without an external security IC.
  • Radar processing: on-chip SPU offload for ADAS applications: The on-chip SPUs offload radar signal processing from the TriCore™ cores, maintaining real-time control loop performance under peak sensor data loads.
  • Qualification: AEC-Q100: The AURIX™ TC3x is qualified to Automotive Electronics Council Q100 (AEC-Q100), confirming suitability for automotive operating environments.
Learn more about functional safety

Domain control, ADAS, powertrain, and connected car

  • Automotive domain control and data fusion: For domain control units consolidating radar, LIDAR, and camera sensor inputs, the TC37x, TC38x, and TC39x sub-families are recommended because their 4 to 6 TriCore™ cores support parallel ASIL-D-compliant processing within a single device.
  • ADAS: radar, LIDAR, and camera processing: The TC33xTA and TC39xXA sub-families include dedicated SPUs and ADAS-specific peripheral configurations for radar front-end processing that eliminate the need for a discrete radar DSP.
  • Powertrain and electrification: The family supports inverter control, battery management, onboard charger, and DC-DC converter applications, meeting the functional safety requirements of ISO 26262 for high-voltage powertrain systems.
  • Connected car: telematics, gateway, and In-Vehicle charging: Integrated connectivity peripherals support telematics units and connected gateways. The integrated HSM with Full EVITA addresses UN R155 cybersecurity compliance requirements, covering secure over-the-air update and in-vehicle network authentication without external security IC.
Learn more about automotive application

How to choose an AURIX™ TC3x sub-family for your design

Step 1: Define core count

For concurrent execution of safety monitoring, motor control, and communication, select TC37x, TC38x, or TC39x (4–6 cores). For single-domain control, choose TC32x or TC33x sub-families.

Step 2: Confirm functional safety level

For ISO 26262 ASIL-D applications (domain control, steering, airbag), select a sub-family with a confirmed ASIL-D safety manual.

Step 3: Size flash and RAM to software footprint

Select a sub-family with at least 20% headroom above the AUTOSAR stack, combined code, calibration data and bootloader estimate.

Step 4: Match connectivity to system topology

Gigabit Ethernet is available on selected sub-families. CAN FD and LIN are available across the TC3x portfolio.

Step 5: Filter by ADAS features if required

For radar processing, select sub-families with integrated SPUs (TC33xTA, TC39xXA). Use the AURIX™ TC3x parametric selection tool:

Parameter: Sub-Family

  • 1-3 cores, single domain: TC32x, TC33x
  • 4-6 cores, ASIL-D: TC37x, TC38x, TC39x
  • Radar SPU : TC33xTA, TC39xXA

TriCore™ architecture, migration, PDH ecosystem, and myICP

  • TriCore™ architecture: unified real-time processing core
    • TriCore™ is a unified 32-bit microcontroller-DSP architecture, combining microcontroller real-time capability, DSP computational throughput, and RISC load-store code density in a reprogrammable core. It supports 16-bit and 32-bit instruction formats, 4 GB of address space, and hardware memory protection. All TC3x sub-families share a common TriCore™ ISA, protecting software investment across the portfolio.
  • Pin compatibility with AURIX™ TC2x for migration continuity
    • The AURIX™ TC3x family is pin-compatible with the AURIX™ TC2x. This allows engineers to reuse PCB layouts and reduce re-qualification effort when migrating from TC2x to TC3x.
  • AURIX™ Preferred Design House (PDH) ecosystem
    • Infineon supports designs through a network of PDHs trained in AURIX™ MCU development. Local field application engineers address standard questions; dedicated automotive security experts handle complex safety topics.
  • myICP collaboration platform for technical documentation
    • Engineers can access additional documentation, training, and tools by registering on myICP.
Learn more about AURIX™ Preferred Design Houses
myICP
How to register

Software, eval kits, and technical documentation for TC3x

  • Software, SDKs & Tools: Infineon provides a free Eclipse-based IDE for TC3x application development, low-level driver libraries for peripheral configuration, and AUTOSAR BSW and MCAL packages.
  • Evaluation kits: Evaluation kits are available to support hardware bring-up and software development for TC3x sub-families. Each kit provides a ready-to-test hardware platform, reducing bring-up time at the start of development.
  • Digital collaterals: Datasheets, user manuals, code examples, and presentations are accessible in HTML format via the AURIX™ digital collaterals portal across desktop and mobile devices.
  • Technical documentation via myICP: Additional documentation, training, and tools are available through the myInfineon Collaboration Platform (myICP). To register, sign up at myInfineon and send an access request to AURIX@infineon.com using a company email address.
  • Microcontroller training and video hub: Expert tutorials and hands-on guides for AURIX™ Development Studio and TC3x peripheral configuration are available through the Microcontroller Training and Video Hub.
Discover AURIX™ digital collaterals
Microcontroller training and video hub
Documents