Active and preferred
RoHS Compliant

S70KL1283GABHV023

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S70KL1283GABHV023
S70KL1283GABHV023
Data Sheet

Product details

  • Density
    128 MBit
  • Family
    KL-3
  • Initial Access Time
    35 ns
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 200
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM
Recommended
OPN
S70KL1283GABHV023
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S70KL1283GABHV023 is a 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) with an Octal xSPI DDR interface using an 8-bit DQ bus plus RWDS and CS#. It supports up to 200 MHz clock and 400 MBps throughput, with 35 ns maximum access time. The 3.0 V-only S70KL family operates from 2.7 V to 3.6 V and supports hybrid sleep, deep power-down, and partial array refresh modes. It is offered in a 24-ball FBGA package.

Features

  • Octal xSPI interface
  • 1.7 V to 2.0 V VCC/VCCQ
  • 2.7 V to 3.6 V VCC/VCCQ
  • 200 MHz maximum clock rate
  • DDR on both clock edges
  • Throughput up to 400 MBps
  • 8-bit DQ[7:0] data bus
  • RWDS strobe and write data mask
  • Optional differential clock CK/CK#
  • Optional DCARS read strobe
  • Linear and wrapped burst modes
  • Hybrid Sleep and Deep Power Down

Benefits

  • Octal DDR boosts system bandwidth
  • 400 MBps supports fast frame buffers
  • 200 MHz fits high-speed controllers
  • 8-bit bus reduces signal routing
  • RWDS eases DDR timing margins
  • DCARS improves DDR read eye margin
  • Wrapped bursts reduce access latency
  • Burst modes match cache or streaming
  • Sleep/DPD lowers standby power
  • Partial refresh cuts idle refresh power
  • Dual-voltage fits 1.8 V or 3.0 V rails
  • RESET# enables quick fault recovery

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }