Active and preferred
RoHS Compliant
Lead-free

S28HS02GTFPBHB153

Data Sheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S28HS02GTFPBHB153
S28HS02GTFPBHB153
Data Sheet

Product details

  • Classification
    ISO 26262-compliant
  • Density
    2 GBit
  • Family
    HS-T
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    166 / 166
  • Interfaces
    Octal
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature
    -40 °C to 105 °C
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Automotive
Recommended
OPN
S28HS02GTFPBHB153
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-24801)
Packing Size 2000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S28HS02GTFPBHB153 is a 2 Gb SEMPER™ NOR Flash with a high-speed octal interface, operating at 1.7 V to 2.0 V (HS-T) in a 24-ball BGA package. It supports up to 332 MBps DDR and 166 MBps SDR read rates. Functional safety is enabled by ISO 26262 ASIL-B compliance and AEC-Q100 qualification. ECC, CRC, and SafeBoot features ensure data integrity, while Endurance Flex architecture provides high endurance and long retention for automotive and industrial applications.

Features

  • Infineon 45-nm MIRRORBIT technology
  • Octal and SPI interface options
  • JEDEC JESD251 xSPI compliant
  • SDR up to 166 MBps, DDR up to 332 MBps
  • Configurable 256 or 512 byte page buffer
  • Flexible sector architecture: uniform/hybrid
  • Built-in ECC (SECDED) for data integrity
  • Functional safety: ISO26262 ASIL B compliant
  • CRC error detection and SafeBoot recovery
  • 2,560,000 program-erase cycles (main array)
  • 25 years minimum data retention
  • Hardware reset via CS# or RESET# pin

Benefits

  • Dual-bit storage increases memory density
  • High-speed read/write boosts system speed
  • Flexible interface eases system integration
  • Reliable data with ECC and CRC protection
  • Functional safety supports critical systems
  • Long retention ensures data reliability
  • Multiple sector options fit varied needs
  • Fast programming with large page buffer
  • SafeBoot enables robust failure recovery
  • High endurance lowers maintenance cost
  • JEDEC compliance ensures compatibility
  • Hardware reset simplifies system design

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }