CY7C1645KV18-400BZXI
Active and preferred
RoHS Compliant

CY7C1645KV18-400BZXI

Data Sheet
package
ea.
in stock

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CY7C1645KV18-400BZXI
CY7C1645KV18-400BZXI
ea.
Data Sheet

Product details

  • Architecture
    QDR-II+
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+
  • Frequency
    400 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C1645KV18-400BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
The CY7C1645KV18-400BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM organized as 4 M × 36 with separate read and write ports to eliminate data-bus turnarounds. It supports four-word burst transfers with 2-cycle read latency (or 1-cycle QDR I mode via DOFF), DDR I/O at up to 400 MHz clock (800 MT/s), echo clocks and QVLD, HSTL I/Os, and an on-chip PLL (120 MHz to max freq), plus JTAG 1149.1.

Features

  • 144-Mbit QDR II+ burst SRAM
  • Separate read and write ports
  • DDR I/O; data at 900 MHz max
  • 450 MHz max clock frequency
  • Four-word burst per access
  • Read latency 2 cycles (DOFF high)
  • QDR I mode: 1-cycle latency (DOFF)
  • Two input clocks K and K
  • Echo clocks CQ and CQ
  • QVLD valid-data output
  • PLL locks after 20 µs stable clock
  • Programmable output impedance (ZQ)

Benefits

  • Eliminates bus turnaround delays
  • Enables high memory bandwidth
  • Cuts address bus frequency needs
  • Simplifies timing with echo clocks
  • Easier data capture with QVLD
  • Pipelines read/write independently
  • Supports read-after-write coherency
  • Adapts to line impedance for SI
  • Reduces board tuning across PVT
  • Faster bring-up via auto PLL lock
  • Depth expansion without wait states
  • Simplifies test with JTAG port

Applications

Documents

Design resources

Partner solutions

Developer community

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