S70KL1283DPBHI020
not for new design
RoHS Compliant
Lead-free

S70KL1283DPBHI020

Datasheet
package

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S70KL1283DPBHI020
S70KL1283DPBHI020
Datasheet


Product details

  • Density
    128 MBit
  • Family
    KL-3
  • Initial Access Time
    36 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    xSPI (Octal)
  • Lead Ball Finish
    N/A
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.7 V to 3.6 V
  • Operating Voltage
    3 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    See roadmap
  • Qualification
    Industrial
  • Technology
    HYPERRAM

OPN
S70KL1283DPBHI020
Product Status not for new design
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW

Product Status not for new design
Infineon Package
PG-BGA-24
Package Name BGA-24 (002-15550)
Packing Size 3380
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
The S70KL1283DPBHI020 is a 128 Mb HYPERRAM™ self-refresh DRAM (PSRAM) for high-bandwidth external memory over an octal xSPI DDR interface with RWDS strobe. It supports 166 MHz clock operation, delivering DDR transfers on both clock edges. The device operates from 2.7 V to 3.6 V VCC/VCCQ over –40°C to +85°C (Industrial) and comes in a 24-ball FBGA (5 × 5, 1.00 mm pitch). Deep Power Down and Hybrid Sleep are supported.

Features

  • Octal xSPI interface
  • 1.7 V to 2.0 V VCC/VCCQ
  • 2.7 V to 3.6 V VCC/VCCQ
  • 200 MHz maximum clock rate
  • DDR on both clock edges
  • Throughput up to 400 MBps
  • 8-bit DQ[7:0] data bus
  • RWDS strobe and write data mask
  • Optional differential clock CK/CK#
  • Optional DCARS read strobe
  • Linear and wrapped burst modes
  • Hybrid Sleep and Deep Power Down

Benefits

  • Octal DDR boosts system bandwidth
  • 400 MBps supports fast frame buffers
  • 200 MHz fits high-speed controllers
  • 8-bit bus reduces signal routing
  • RWDS eases DDR timing margins
  • DCARS improves DDR read eye margin
  • Wrapped bursts reduce access latency
  • Burst modes match cache or streaming
  • Sleep/DPD lowers standby power
  • Partial refresh cuts idle refresh power
  • Dual-voltage fits 1.8 V or 3.0 V rails
  • RESET# enables quick fault recovery

Applications

Smart thermostat
Documents

Design resources

Partner solutions

Developer community