Active and preferred
RoHS Compliant
Lead-free

S28HS512TGABHM010

High-speed, ISO 26262-compliant 512Mbit HS-T memory with 400MByte/s interface bandwidth, ideal for automotive applications
Data Sheet
package
ea.
in stock

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S28HS512TGABHM010
S28HS512TGABHM010
ea.
Data Sheet

Product details

  • Classification
    ISO 26262-compliant
  • Density
    512 MBit
  • Family
    HS-T
  • Interface Bandwidth
    400 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    200 / 200
  • Interfaces
    Octal
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Qualification
    Automotive
Recommended
OPN
S28HS512TGABHM010
Product Status active and preferred
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 676
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-24
Package Name FBGA-24 (002-15550)
Packing Size 676
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
S28HS512TGABHM010 is a 512 Mbit SEMPER™ NOR Flash (HS-T) with octal interface (8S-8S-8S, 8D-8D-8D) for automotive code and data storage. It runs from 1.7 V to 2.0 V over -40°C to 125°C and supports 200 MHz SDR/DDR clocks for up to 400 MByte/s bandwidth. ISO 26262-compliant features include ECC (SECDED), interface CRC, data integrity CRC, SafeBoot, and Endurance Flex partitioning.

Features

  • 45-nm MIRRORBIT™ stores 2 bits/cell
  • Uniform or hybrid sector architecture
  • 256 or 512-byte program buffer
  • 1024-byte OTP secure silicon array
  • Octal 8S-8S-8S and 8D-8D-8D
  • JEDEC JESD251 xSPI compliant
  • Data strobe (DS) for read capture
  • ECC on 16-byte units, SECDED
  • SafeBoot status detects init faults
  • AutoBoot outputs data after reset
  • LBP and ASP sector protection
  • Hardware or software reset support

Benefits

  • Higher density with fewer cells
  • Fits boot code and data layouts
  • Faster page program transactions
  • Stores IDs and secrets securely
  • High throughput on few signal pins
  • Easier host support via xSPI
  • Improves timing margin at high speed
  • Reduces bit errors in stored code
  • Enables recovery after bad power-up
  • Cuts boot time and host firmware steps
  • Prevents unauthorized code changes
  • Simplifies robust system reset design

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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