Active and preferred
RoHS Compliant
Lead-free

CYT2BL4CAAQ0AZEGST

Data Sheet
package

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CYT2BL4CAAQ0AZEGST
CYT2BL4CAAQ0AZEGST
Data Sheet

Product details

  • 16bit TCPWM (Motor control)
    12
  • 16bit TCPWM
    63
  • 32bit TCPWM
    8
  • ADC Channel
    34
  • ASIL/SIL support
    ASIL-B
  • CAN-FD
    7
  • Classification
    ISO 26262-compliant
  • CXPI
    3
  • Cybersecurity Classification
    ISO 21434-compliant
  • Debug Interface
    SWD/JTAG/Trace
  • DMA Channels
    92/44/4
  • eMMC
    0
  • eSHE/HSM
    HSM
  • Ethernet Ports
    0
  • Ethernet speed
    NA
  • External Interrupt channel
    63
  • Flash Security
    Yes
  • Flash
    4160 kByte
  • FlexRayTM
    0
  • Floating Point Unit
    Single precision
  • GPIO
    63
  • I2S
    NA
  • LIN
    9
  • Main Core frequency
    160 MHz
  • Main Core type/Crypto Core type
    ARM_CM4F/CM0+
  • MPU
    Yes
  • Operating temperature range TA
    -40°C to 125°C
  • PPU
    Yes
  • RC-OSC
    Yes
  • RTC channel
    1
  • SCB Blocks
    8
  • Smart IOs
    14
  • SMIF (SPI/HyperBus)
    NA
  • SRAM
    512 kByte
  • Supply Voltage
    2.7 to 5.5
  • Temperature sensor
    Yes
  • Watchdog
    Yes
  • Work Flash
    128 kByte
Recommended
OPN
CYT2BL4CAAQ0AZEGST
Product Status active and preferred
Infineon Package
PG-LQFP-80
Package Name LQFP-80 (002-11501)
Packing Size 500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-LQFP-80
Package Name LQFP-80 (002-11501)
Packing Size 500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The CYT2BL4CAAQ0AZEGST is an automotive microcontroller from the TRAVEO T2G CYT2BL series. It features dual-core ARM Cortex-M4F (160 MHz) and Cortex-M0+ architecture, 4160 kByte flash, 128 kByte work flash, and 512 kByte SRAM. ASIL-B and ISO 26262 compliance, ISO 21434-ready cybersecurity, and HSM ensure robust safety and security. Operating from 2.7 V to 5.5 V across -40°C to 125°C, it integrates 7 CAN-FD channels.

Features

  • Dual Arm Cortex-M4F (160 MHz) and M0+
  • 4160 KB code-flash, 512 KB SRAM, 128 KB
  • Crypto engine: AES, 3DES, RSA, ECC, SHA, TRNG
  • Up to 8 CAN FD channels, ISO 11898-1:2015
  • Up to 8 SCB (I2C, SPI, UART), 12 LIN channels
  • 12-bit SAR ADC, 1 Msps, up to 64 channels
  • Functional safety: MPU, PPU, watchdog, ECC
  • Low-power modes: Active, Sleep, Deep Sleep,
  • 2.7 V to 5.5 V operation, multiple clock
  • DMA controllers: P-DMA0 (92 ch), P-DMA1
  • Debug: SWD/JTAG, on-chip debug, industry
  • Smart I/O, up to 148 GPIO_STD, 4 GPIO_ENH

Benefits

  • Dual CPUs enable real-time and control tasks
  • Large flash/SRAM supports complex
  • Crypto engine ensures data security
  • CAN FD, SCB, LIN enable flexible connectivity
  • High-speed ADC enables precise sensor
  • Safety features protect against system faults
  • Multiple low-power modes reduce energy use
  • Wide voltage range suits diverse systems
  • DMA boosts data throughput and efficiency
  • On-chip debug simplifies development
  • Smart I/O, many GPIOs ease system integration
  • Standards compliance ensures broad

Applications

Documents

Documents

Design resources

Partner solutions

Developer community

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