CY7C4142KV13-933FCXI
Active and preferred
RoHS Compliant
Lead-free

CY7C4142KV13-933FCXI

Datasheet
package

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CY7C4142KV13-933FCXI
CY7C4142KV13-933FCXI
Datasheet


Product details

  • Architecture
    QDR-IV
  • Bank Switching
    Y
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    Y
  • Family
    QDR-IV
  • Frequency
    933 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.26 V to 1.34 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Read Latency (Cycles)
    8

Recommended
OPN
CY7C4142KV13-933FCXI
Product Status active and preferred
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 60
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 60
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
TW
CY7C4142KV13-933FCXI is a 144-Mbit QDR-IV XP SRAM configured as 4M × 36 with two independent bidirectional DDR data ports and a single DDR address bus with SDR controls. It supports up to 933 MHz operation (1866 MT/s). Eight internal banks enable one access per bank per cycle. It uses 1.3 V VDD and 1.1 V or 1.2 V POD VDDQ, and integrates ODT, ECC, address parity, and JTAG.

Features

  • 144-Mbit QDR-IV XP SRAM
  • Total RTR 2132 MT/s
  • Max operating frequency 1066 MHz
  • Dual independent bidir DDR ports
  • Single DDR addr bus, SDR control
  • Eight banks, 1 access/bank/cycle
  • Two-word burst for all accesses
  • On-die termination, programmable
  • ZQ self-cal output impedance
  • Bus inversion for addr/data buses
  • Address parity with PE# error flag
  • On-chip ECC, SER <0.01 FIT/Mb

Benefits

  • 2132 MT/s boosts random throughput
  • 1066 MHz enables low-latency ops
  • Concurrent reads/writes on 2 ports
  • Shared addr bus reduces routing
  • 8 banks sustain high transaction rate
  • 2-word burst improves data bandwidth
  • ODT eases signal integrity design
  • ZQ cal keeps stable I/O margins
  • Bus inversion cuts SSN and power
  • Parity flag speeds fault isolation
  • ECC reduces soft-error data faults
  • <0.01 FIT/Mb improves reliability

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