CY7C25702KV18-550BZXI
Active and preferred
RoHS Compliant

CY7C25702KV18-550BZXI

Datasheet
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CY7C25702KV18-550BZXI
CY7C25702KV18-550BZXI
Datasheet

Product details

  • Architecture
    DDR-II+ CIO, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    DDR-II+ CIO, ODT
  • Frequency
    550 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C25702KV18-550BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 680
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 680
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C25702KV18-550BZXI is a 72-Mbit DDR II+ synchronous pipelined SRAM (2M × 36) with two-word burst architecture. It supports up to 550 MHz clock with 1100 MHz DDR data transfers and 2.5-cycle read latency (DOFF HIGH). Dual input clocks (K/K), echo clocks (CQ/CQ), QVLD data-valid, and IEEE 1149.1 JTAG aid high-speed capture and test. Supplies: 1.7 V to 1.9 V VDD, 1.4 V to VDD VDDQ, with on-die termination.

Features

  • 72-Mbit DDR II+ SRAM
  • Two-word burst architecture
  • 550 MHz clock, 1100 MHz DDR data
  • 2.5-cycle read latency (DOFF=HIGH)
  • DDR I mode: 1-cycle latency
  • Dual input clocks K/K
  • Echo clocks CQ/CQ
  • QVLD data-valid indicator
  • ODT on D, BWS, and K/K inputs
  • PLL: 120 MHz to fMAX, 20 us lock
  • Byte write via BWS[x:0]
  • ZQ RQ 175–350 ohm, ±15% match

Benefits

  • 1100 MHz DDR boosts bandwidth
  • Two-word burst cuts addr toggling
  • 2.5-cycle latency fits pipelines
  • DDR I mode eases legacy timing
  • K/K improves DDR timing margin
  • CQ/CQ simplify data capture
  • QVLD reduces strobe tuning effort
  • ODT cuts external resistors and area
  • ZQ matching improves signal integrity
  • PLL improves read data placement
  • Byte writes avoid read-modify-write
  • Power-down lowers standby draw

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