CY7C1520KV18-333BZXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1520KV18-333BZXI

Datasheet
package
ea.
in stock

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CY7C1520KV18-333BZXI
CY7C1520KV18-333BZXI
ea.
Datasheet


Product details

  • Density
    72 MBit
  • Family
    DDR-II CIO
  • Frequency
    333 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2M x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial

Recommended
OPN
CY7C1520KV18-333BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH
Country of Diffusion (CoD)
TW
ea.
in stock
CY7C1520KV18-333BZXI is a 72-Mbit (2M × 36) DDR-II synchronous pipelined SRAM with two-word burst architecture. It supports 333 MHz clocks with DDR transfers to 666 MHz and offers 1.5-cycle read latency (DOFF HIGH) or 1-cycle DDR-I-compatible latency (DOFF LOW). It uses 1.7 V to 1.9 V VDD with 1.4 V to VDD VDDQ, and comes in a 165-ball FBGA (13 × 15 × 1.4 mm) Pb-free industrial package.

Features

  • 72-Mbit DDR-II sync SRAM
  • 333 MHz clock, 666 MHz data xfer
  • Two-word burst, 1-bit counter
  • 1.5-cycle read latency (DOFF HI)
  • 1-cycle read latency (DOFF LO)
  • Dual input clocks K/K
  • Dual output clocks C/C
  • Echo clocks CQ/CQ
  • Byte write via BWS signals
  • ZQ sets output impedance
  • PLL runs 120 MHz to fMAX
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • High bandwidth at 333 MHz clocks
  • Cuts addr bus rate with 2-word burst
  • Latency option fits DDR-I/DDR-II
  • Improves DDR timing with K/K clocks
  • Reduces skew using C/C clocks
  • Simplifies capture with CQ/CQ clocks
  • Byte writes avoid read-modify-write
  • Impedance control improves SI
  • PLL stabilizes high-speed timing
  • Depth expansion without wait states
  • Pipeline starts every K rising edge
  • Eases board test with JTAG scan

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