CY7C1481BV33-133AXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1481BV33-133AXI

Datasheet
package

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CY7C1481BV33-133AXI
CY7C1481BV33-133AXI
Datasheet


Product details

  • Architecture
    Standard Sync, Flow-through
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1

Recommended
OPN
CY7C1481BV33-133AXI
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TW
Country of Diffusion (CoD)
US
CY7C1481BV33-133AXI is a 72-Mbit (2M × 36) synchronous flow-through SRAM for secondary cache and high-speed processor interfaces. It supports 133 MHz operation with 6.5 ns clock-to-data access and 2-1-1-1 burst reads using an on-chip 2-bit wraparound counter (linear or interleaved via MODE). Common I/O, byte writes (BWx/BWE) and global write (GW), JTAG, and ZZ sleep mode are included.

Features

  • 133 MHz synchronous bus operation
  • 6.5 ns max tCDV from clock rise
  • 2M × 36 common I/O architecture
  • 2-bit on-chip burst counter
  • Linear or interleaved burst via MODE
  • High-performance 2-1-1-1 access rate
  • Separate ADSP and ADSC strobes
  • Byte writes via BWx plus BWE
  • Global write (GW) writes all bytes
  • Asynchronous OE for tri-state control
  • ZZ sleep mode, 2-cycle entry/exit
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • 133 MHz supports fast cache SRAM
  • 6.5 ns reduces read latency
  • 36-bit I/O fits wide data paths
  • Burst counter cuts address overhead
  • Select burst order per CPU needs
  • 2-1-1-1 boosts sustained bandwidth
  • ADSP/ADSC simplify bus control
  • Byte writes reduce data toggling
  • Global write eases full-word writes
  • Async OE enables shared data bus
  • Sleep mode lowers standby current
  • JTAG speeds board test and debug

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