CY7C1471BV33-133BZI
Active and preferred

CY7C1471BV33-133BZI

Data Sheet
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CY7C1471BV33-133BZI
CY7C1471BV33-133BZI
Data Sheet

Product details

  • Architecture
    NoBL, Flow-through
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    72 MBit
  • ECC
    N
  • Family
    NoBL
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    2Mb x 36
  • Peak Reflow Temp
    220 °C
  • Qualification
    Industrial
Recommended
OPN
CY7C1471BV33-133BZI
Product Status active and preferred
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant No
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Product Status
Active
Infineon Package
P -BGA-165
Package Name FBGA-165 (51-85165)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1471BV33-133BZI is a 72-Mbit synchronous flow-through burst SRAM (2M × 36) using NoBL architecture to eliminate dead cycles on write-to-read transitions. It supports 133 MHz operation with 6.5 ns clock-to-data valid, registered inputs, and pipelined read/write/deselect cycles. Features include up to 4-word linear or interleaved burst, byte write (BWX), three chip enables plus OE, and ZZ sleep mode.

Features

  • 72-Mbit sync burst SRAM
  • NoBL eliminates dead cycles
  • Up to 133 MHz, 7.5 ns cycle
  • Data transferred every clock
  • 6.5 ns clock-to-output (tCDV)
  • Registered synchronous inputs
  • Byte write using BWX + WE
  • Linear or interleaved burst order
  • 3 chip enables (CE1/CE2/CE3)
  • Asynchronous OE tri-state control
  • Auto power-down via ZZ or CE
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • Back-to-back R/W boosts throughput
  • Zero wait states cut bus stalls
  • 133 MHz supports fast processing
  • Every-clock data raises bandwidth
  • 6.5 ns tCDV reduces read latency
  • Registered inputs ease timing closure
  • Byte writes reduce write bandwidth
  • Burst modes match CPU/DSP bursts
  • 3 chip enables simplify expansion
  • OE tri-state eases bus sharing
  • Power-down reduces idle power
  • JTAG speeds board test and debug

Applications

Documents

Design resources

Partner solutions

Developer community

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