CY7C1470EV33-1X11I
Active and preferred
RoHS Compliant
Lead-free

CY7C1470EV33-1X11I

Data Sheet

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CY7C1470EV33-1X11I
CY7C1470EV33-1X11I
Data Sheet

Product details

  • Density
    72 MBit
  • Interfaces
    Parallel
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.135 V to 3.6 V
  • Qualification
    Industrial
Recommended
OPN
CY7C1470EV331X11IX5SA1
Product Status active and preferred
Infineon Package --
Package Name N/A
Packing Size 6
Packing Type WAFFLE PACK
Moisture Level N/A
Moisture Packing NON DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package --
Package Name -
Packing Size 6
Packing Type WAFFLE PACK
Moisture Level -
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1470EV33-1X11I is a 72-Mbit synchronous pipelined burst SRAM with No Bus Latency (NoBL) architecture for zero-wait-state back-to-back reads/writes. It supports bus speeds up to 250 MHz with fully registered inputs/outputs and 3.0 ns clock-to-output. Operates from 3.135 V to 3.6 V core with 3.135 V to VDD or 2.375 V to 2.625 V I/O supply and offers byte write plus ZZ sleep mode.

Features

  • 72-Mbit sync pipelined SRAM
  • No Bus Latency (NoBL) logic
  • 250 MHz bus ops, zero wait states
  • Registered inputs and outputs
  • Linear or interleaved burst order
  • Byte write with BWx byte selects
  • VDD 3.135 V to 3.6 V single rail
  • VDDQ I/O: 2.5 V or 3.3 V
  • 3.0 ns clock-to-output (250 MHz)
  • ZZ sleep mode and Stop Clock
  • IEEE 1149.1 JTAG boundary scan
  • Neutron SER: 361 FIT/Mb typ, 25C

Benefits

  • Run back-to-back ops with no stalls
  • More throughput each clock cycle
  • Drop-in path for ZBT designs
  • Predictable timing simplifies closure
  • Burst support fits streaming data
  • Byte writes cut rewrite bandwidth
  • Single-rail core eases power design
  • Direct 2.5/3.3 V logic connection
  • 3.0 ns tCO reduces read latency
  • Sleep/stop clock cuts idle power
  • JTAG simplifies board test & debug
  • Lower soft-error risk in systems

Applications

Documents

Design resources

Partner solutions

Developer community

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