CY7C1061GN30-10ZXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1061GN30-10ZXI

Data Sheet
package

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CY7C1061GN30-10ZXI
CY7C1061GN30-10ZXI
Data Sheet

Product details

  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage max
    3.6 V
  • Operating Voltage
    2.2 V
  • Organization (X x Y)
    2M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns
Recommended
OPN
CY7C1061GN30-10ZXI
Product Status active and preferred
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 192
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 192
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1061GN30-10ZXI is a 16-Mbit (1M × 16) asynchronous CMOS SRAM with 10 ns access time. It operates from 2.2 V to 3.6 V over the industrial range (−40°C to +85°C) and supports automatic power-down when deselected. It provides 20 address lines (A0–A19), 16-bit I/O with BLE/BHE byte writes, TTL-compatible levels, 1.0 V data retention, and a Pb-free 48-pin TSOP I (ZX) package for bus-oriented memory expansion.

Features

  • 1,048,576 × 16 SRAM array
  • tAA 10 ns/15 ns access time
  • VCC operating 2.2 V to 3.6 V
  • 1.0 V data retention (VDR min)
  • Byte write via BLE and BHE pins
  • Dual chip enables: CE1 and CE2
  • Automatic power-down when deselect
  • OE-controlled output High-Z state
  • ICC 90 mA typ at 100 MHz
  • ISB2 20 mA typ standby (CMOS)
  • IIX/IOZ leakage ±1 µA
  • ESD >2001 V (MIL-STD-883)

Benefits

  • 16-bit bus increases throughput
  • 10 ns access supports fast reads
  • 2.2–3.6 V fits common power rails
  • Retention at 1.0 V saves state
  • Byte writes cut write bandwidth
  • Dual CE eases memory expansion
  • Auto power-down cuts idle power
  • High-Z outputs simplify bus share
  • Low leakage improves standby power
  • ESD robustness improves uptime
  • CMOS SRAM enables simple interface
  • Defined timing reduces design risk
Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }