CY7C1061GN18-15ZSXI
Active and preferred
RoHS Compliant

CY7C1061GN18-15ZSXI

Datasheet
package

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CY7C1061GN18-15ZSXI
CY7C1061GN18-15ZSXI
Datasheet


Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    1.65 V to 2.2 V
  • Operating Voltage range
    1.65 V to 2.2 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    15 ns

Recommended
OPN
CY7C1061GN18-15ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-54
Package Name TSOP-II-54 (51-85160)
Packing Size 108
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-54
Package Name TSOP-II-54 (51-85160)
Packing Size 108
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1061GN18-15ZSXI is a 16-Mbit (1M × 16) fast asynchronous CMOS SRAM with 15 ns max access time. It operates from a 1.65 V to 2.2 V supply and supports byte writes via BLE/BHE with OE and WE control. Automatic chip-enable power-down reduces standby current (ISB2 typ 20 mA, max 30 mA), while operating ICC is 90 mA typ (110 mA max) at 100 MHz. It is offered in a Pb-free 54-pin TSOP II package (industrial grade).

Features

  • 1M words x 16-bit SRAM array
  • 10 ns/15 ns address access (tAA)
  • 10 ns/15 ns read cycle time (tRC)
  • OE access 5 ns/8 ns (tDOE)
  • VCC 2.2 V to 3.6 V operation
  • Data retention down to 1.0 V (VDR)
  • Data retention current 30 mA max
  • ICC 90 mA typ at 100 MHz
  • Auto power-down when deselected
  • TTL-compatible I/O levels
  • Dual chip enables (CE1, CE2)
  • Two byte enables (BLE, BHE)

Benefits

  • 16-bit bus boosts bandwidth
  • 10 ns class reads cut latency
  • Fast OE gives quick bus turn-on
  • 2.2-3.6 V fits common rails
  • 1.0 V retention saves standby power
  • Auto power-down reduces idle draw
  • TTL levels ease logic interfacing
  • CE1/CE2 simplify memory expansion
  • Byte enables support 8-bit writes
  • Low leakage supports low-power idle
  • High-Z outputs prevent bus contention
  • Clear timing specs speed design-in
Documents

Design resources

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