CY7C1061GE30-10ZXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1061GE30-10ZXI

Datasheet
package
ea.
in stock

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CY7C1061GE30-10ZXI
CY7C1061GE30-10ZXI
ea.
Datasheet


Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns

Recommended
OPN
CY7C1061GE30-10ZXI
Product Status active and preferred
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 192
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Country of Assembly (CoA)
TH,TW
Country of Diffusion (CoD)
TW
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-48
Package Name TSOP-I-48 (51-85183)
Packing Size 192
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
Country of Assembly (CoA)
TH,TW
Country of Diffusion (CoD)
TW
ea.
in stock
CY7C1061GE30-10ZXI is a 16-Mbit (1M × 16) fast asynchronous SRAM with embedded ECC and an ERR output that flags single-bit error detection/correction on reads. It operates from 2.2 V to 3.6 V over −40°C to +85°C, with 10 ns access time. It supports single chip enable, BHE/BLE byte writes, automatic CE power-down, and is offered with typical ICC 90 mA at 100 MHz in a Pb-free 48-pin TSOP I package.

Features

  • 16-Mbit (1M x 16) async SRAM
  • Embedded ECC single-bit correction
  • ERR output flags corrected 1-bit
  • tAA access time 10 ns/15 ns
  • 16-bit I/O with BLE/BHE byte writes
  • Single or dual chip-enable inputs
  • Auto CE power-down (ISB1/ISB2)
  • ICC typ 90 mA at 100 MHz
  • 1.0 V data retention mode
  • TTL-compatible I/O levels
  • Ambient temp -40°C to +85°C
  • ESD > 2001 V (MIL-STD-883)

Benefits

  • ECC improves SRAM data integrity
  • ERR pin simplifies error monitoring
  • 10 ns access supports fast reads
  • Byte writes reduce write bandwidth
  • CE options ease system integration
  • Auto power-down cuts standby draw
  • 1.0 V retention lowers backup power
  • TTL levels ease bus interfacing
  • -40°C to +85°C boosts reliability
  • High ESD improves handling margin
  • Lower active current reduces heat
  • Async SRAM simplifies controller logic

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