CY62177G30-55ZXIT
Active and preferred
RoHS Compliant
Lead-free

CY62177G30-55ZXIT

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CY62177G30-55ZXIT
CY62177G30-55ZXIT

Product details

  • Density
    32 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Pure Sn
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    2M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
OPN
CY62177G30-55ZXIT
Product Status active and preferred
Infineon Package
Package Name TSOP-I-48 (51-85183)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
Package Name TSOP-I-48 (51-85183)
Packing Size 1000
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62177G30-55ZXIT is a 32-Mbit (2M x 16 or 4M x 8) asynchronous MoBL SRAM with embedded ECC for single-bit correction. It runs from 2.2 V to 3.6 V over -40°C to 85°C with 55 ns access time. Automatic power-down cuts standby current to 3 µA typical (19 µA max). CMOS/TTL-level I/O and byte enables support 8-bit/16-bit accesses. ZXIT is a Pb-free 48-pin TSOP I, tape-and-reel, industrial grade.

Features

  • 16-Mbit SRAM, 1M x 16 or 2M x 8
  • Embedded ECC corrects 1-bit errors
  • ERR pin flags ECC events (GE30)
  • 55 ns read cycle time (tRC)
  • OE to data valid 25 ns max (tDOE)
  • VCC operating range 2.2 V to 3.6 V
  • 3 µA typ standby, 19 µA max
  • Data retention at 1.5 V
  • ICCDR 3 µA typ, 19 µA max
  • Byte writes via BHE/BLE signals
  • Automatic power-down (ISB1/ISB2)
  • High-Z outputs when deselected

Benefits

  • ECC reduces soft error corruption
  • ERR output eases health monitoring
  • 55 ns access supports fast SRAM reads
  • 25 ns OE timing eases bus timing
  • 2.2–3.6 V VCC fits 3.3 V rails
  • Ultra-low standby cuts idle power
  • 1.5 V retention preserves data off
  • Low ICCDR extends backup supply
  • Byte enables reduce write traffic
  • Auto power-down saves energy
  • High-Z outputs enable bus sharing
  • 16/8-bit modes ease system reuse

Applications

Documents

Design resources

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }