CY62147G30-45B2XI
Active and preferred
RoHS Compliant
Lead-free

CY62147G30-45B2XI

Datasheet
package

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CY62147G30-45B2XI
CY62147G30-45B2XI
Datasheet


Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial

Recommended
OPN
CY62147G30-45B2XI
Product Status active and preferred
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 4800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-VFBGA-48
Package Name VFBGA-48 (51-85150)
Packing Size 4800
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62147G30-45B2XI is a 4-Mbit (256K × 16) asynchronous CMOS SRAM with embedded ECC. It supports 45 ns access at 2.2 V to 3.6 V over the industrial -40°C to 85°C range. The B2 option uses dual chip enables and provides byte-wide accesses via BHE/BLE plus a byte power-down standby mode. ICC is 20 mA max at f = 22.22 MHz, and standby is 3.5 µA typ (ISB2). It is offered in a Pb-free 48-ball VFBGA.

Features

  • 4-Mbit SRAM, 256K × 16
  • Embedded ECC 1-bit correction
  • 45 ns/55 ns read cycle time tRC
  • 16-bit I/O with BLE/BHE byte en
  • HI-Z outputs when deselected
  • Standby current max 8.7 µA
  • Data retention VDR = 1.0 V
  • ICCDR max 13 µA at VCC = 1.2 V
  • Operating temp –40°C to +85°C
  • ESD >2001 V (MIL-STD-883)
  • Latch-up current >140 mA

Benefits

  • ECC corrects single-bit faults
  • 45/55 ns enables fast access
  • Byte enables cut write activity
  • HI-Z outputs ease bus sharing
  • 8.7 µA max standby saves power
  • 1.0 V retention preserves data
  • 13 µA retention cuts backup load
  • –40°C to +85°C boosts reliability
  • >2001 V ESD improves handling
  • >140 mA latch-up adds robustness
  • Async SRAM avoids DRAM refresh

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Documents

Design resources

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