CY62146EV30LL-45ZSXI
Active and preferred
RoHS Compliant

CY62146EV30LL-45ZSXI

Datasheet
package

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY62146EV30LL-45ZSXI
CY62146EV30LL-45ZSXI
Datasheet


Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns

Recommended
OPN
CY62146EV30LL-45ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 1350
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY62146EV30LL-45ZSXI is a 4-Mbit (256K × 16) CMOS static RAM with a 45 ns speed grade for battery-powered designs. It operates from 2.2 V to 3.6 V over –40°C to +85°C and uses CE, OE, WE plus BLE/BHE byte enables for 8-bit or 16-bit accesses. Automatic CE power-down reduces current when deselected; ICC is 3.5 mA typ at 1 MHz and 20 mA max at fmax, with 2.5 µA typ (7 µA max) standby. Pb-free 44-pin TSOP II.

Features

  • 256K × 16 CMOS SRAM organization
  • 45 ns read/write cycle time
  • 22 ns OE to data valid (tDOE)
  • 2.2 V to 3.6 V VCC operation
  • 3.5 mA typ ICC at 1 MHz
  • 2.5 µA typ standby (ISB)
  • 7 µA max standby (ISB)
  • Auto power-down when CE HIGH
  • 1.5 V data retention supply (VDR)
  • 8.8 µA max retention current
  • Byte write via BHE/BLE enables
  • Outputs tri-state on deselect/OE

Benefits

  • 16-bit SRAM fits MCU data buses
  • 45 ns access supports fast code/data
  • 22 ns OE speeds read turnaround
  • 2.2–3.6 V works with 3 V rails
  • 3.5 mA active extends battery life
  • 2.5 µA standby cuts sleep drain
  • 7 µA max standby eases power budget
  • CE-based power-down saves energy
  • 1.5 V retention keeps data in backup
  • 8.8 µA retention enables small cell
  • Byte enables reduce write power
  • Tri-state outputs simplify bus sharing
Documents

Design resources

Partner solutions

Developer community