CY62146ESL-45ZSXI
Active and preferred
RoHS Compliant

CY62146ESL-45ZSXI

Data Sheet
package
ea.
in stock

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CY62146ESL-45ZSXI
CY62146ESL-45ZSXI
ea.
Data Sheet

Product details

  • Density
    4 MBit
  • Family
    MoBL™ SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) max
    5.5 V
  • Operating Voltage range
    2.2 V to 5.5 V
  • Organization (X x Y)
    256K x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    45 ns
Recommended
OPN
CY62146ESL-45ZSXI
Product Status active and preferred
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 675
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-TSOP-44
Package Name TSOP-II-44 (51-85087)
Packing Size 675
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY62146ESL-45ZSXI is a 4-Mbit (256K × 16) CMOS asynchronous SRAM for low-power embedded storage. It supports 45 ns access and operates from 2.2 V to 3.6 V or 4.5 V to 5.5 V over -40°C to 85°C. Automatic chip-enable power-down reduces standby current to 7 µA max (2.5 µA typ) when CE is HIGH. Typical active current is 3.5 mA at 1 MHz. A 44-pin TSOP-II supports byte writes via BLE/BHE.

Features

  • 256K × 16 CMOS SRAM organization
  • 45 ns read cycle time (tRC)
  • 22 ns OE LOW to data valid
  • Byte write via BHE/BLE enables
  • 2.5 µA typ standby (ISB1/ISB2)
  • 7 µA max standby (ISB1/ISB2)
  • 3.5 mA typ active at 1 MHz
  • Automatic power-down on CE HIGH
  • Output tri-state on CE/OE/BHE/BLE
  • Input/output leakage ±1 µA
  • CIN/COUT max 10 pF at 1 MHz
  • ESD >2001 V (MIL-STD-883)

Benefits

  • 45 ns access supports fast buffers
  • 22 ns OE cuts read latency
  • Byte enables reduce write bandwidth
  • 2.5 µA standby extends battery life
  • 7 µA max eases power budgeting
  • 3.5 mA active lowers energy per op
  • Auto power-down saves idle power
  • Tri-state enables easy bus sharing
  • Low leakage cuts sleep mode drain
  • Low capacitance eases signal timing
  • Robust ESD improves handling yield
  • 16-bit data path boosts throughput

Applications

Documents

Design resources

Partner solutions

Developer community

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