Low Side Drivers
Single channel and dual channel low side gate driver ICs to control MOSFETs and IGBTs
EiceDRIVER™ low side gate driver ICs utilize low-voltage circuitry with the robust technology of high-voltage gate drivers, and the state-of-the-art 0.13-µm process. Our world-class fabrication techniques enable high-current gate drivers for high-power-density applications in industry-standard DSO-8 and small form-factor SOT23 and WSON packages.
We offer comprehensive families of single-low-side and dual-low-side gate driver ICs with flexible options for output current, logic configurations, packages, and protection features such as under-voltage lockout (UVLO), integrated overcurrent protection (OCP), and truly differential inputs (TDI). We also offer automotive qualified low side gate driver.
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Decades of application expertise and technology development at both Infineon and International Rectifier have produced a portfolio of gate driver ICs for use with silicon and wide-bandgap power devices, such as MOSFETs, discrete IGBTs, IGBT modules, SiC MOSFETs and GaN HEMTs. We offer excellent product families of galvanic isolated gate drivers, automotive qualifies gate drivers, 200 V, 500-700 V, 1200 V level shift gate drivers, and non-isolated low-side drivers.
Our portfolio spans a variety of configurations, voltage classes, isolation levels, protection features, and package options. State-of-the-art discrete switch families require tuning of gate drive circuits to take full advantage of their capacity and capabilities. An optimum gate drive configuration is essential for all power switches, whether they are in discrete form or in a power module.
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In this training, we will focus on our low-side gate driver family – 1ED4417x and on its target applications. With this information, you will be able to grow your businesses by winning new designs and customers.
With this training, you will learn how to calculate a gate resistance value for an IGBT application, how to identify suitable gate driver ICs based on peak current and power dissipation requirements, and how to fine-tune the gate resistance value in laboratory environment based on worst case conditions.