Drain-source breakdown voltage explained

A power MOSFET is a metal-oxide-semiconductor field effect transistor: a gate terminal sits on a thin gate oxide over the semiconductor, and a gate voltage above the threshold voltage of MOSFET devices forms a conductive channel that lets drain current flow. The behaviour of this MOS transistor is captured by a handful of standard MOSFET formulas.

These MOSFET equations — sometimes written out as the full MOSFET transistor equations — include the drain-current formula that links current to gate voltage. For choosing a part, though, one rating built into the same MOS structure is the single most important one to get right: the drain-source breakdown voltage.

N-type enhancement mode planar MOSFET

N-type enhancement mode planar MOSFET

The drain-source breakdown voltage, written V(BR)DSS (sometimes BVDSS), is the highest drain-to-source voltage a MOSFET can block in the off state before it breaks down. Every power MOSFET carries this rating, and it is one of the first numbers a designer checks. To understand what is happening inside the device when it conducts and blocks, see how does a MOSFET work.

If the drain-source voltage rises above V(BR)DSS, very high electric fields build up across the reverse-biased PN junctions inside the device. Through a process called impact ionization, these fields generate electron-hole pairs that multiply rapidly — the avalanche effect. The result is a sharp rise in current, high power dissipation, a fast temperature rise, and potential destruction of the device.

One detail matters for reliable design: the V(BR)DSS figure on a datasheet is a guaranteed minimum across manufacturing tolerances. Individual parts may actually break down at a somewhat higher voltage, but a robust design always assumes the worst-case datasheet value rather than the typical behaviour of a single sample.

This article focuses on silicon power MOSFETs. Wide-bandgap devices such as SiC MOSFETs and GaN HEMTs follow different avalanche behaviour and temperature coefficients, and should be evaluated against their own datasheet specifications rather than the rules of thumb given here.

Where to find Vds on a MOSFET datasheet

A MOSFET datasheet usually shows the voltage rating in two related places, and it helps to know the difference:

  • Drain-source voltage (VDS) appears in the Absolute Maximum Ratings table — for example 30 V, 60 V, or 100 V. This is the headline "voltage class" of the part and the value you typically use to shortlist devices.
  • Drain-source breakdown voltage (V(BR)DSS) appears in the Static / Electrical Characteristics table as a guaranteed minimum, measured under defined conditions — typically at VGS = 0 V and a small test current such as ID = 1 mA, at 25 °C.

In practice, manufacturers set the Absolute Maximum VDS rating equal to the guaranteed minimum V(BR)DSS — they are not two independent specifications for two different things, but the same voltage limit shown in two places for two different purposes: one as a hard maximum rating, the other as a measured, guaranteed electrical characteristic.

For example, in Infineon's walkthrough of an OptiMOS™ datasheet, the breakdown voltage is specified as a 60 V minimum at VGS = 0 V and ID = 1 mA. A step-by-step explanation of every datasheet parameter and diagram is available in the Infineon OptiMOS Power MOSFET datasheet explanation.

Understanding the temperature impact on the rating

Breakdown voltage is not a fixed number — it changes with junction temperature. V(BR)DSS has a positive temperature coefficient, so it rises roughly linearly as the device gets hotter, across the full operating range (for example −55 °C to +175 °C). Datasheets show this dependence in a dedicated graph.

The practical takeaway is the opposite of what many beginners expect: because the rating increases with temperature, the lowest breakdown voltage occurs at the lowest temperature. The 25°C datasheet minimum is effectively the worst case under normal conditions, and cold-start situations deserve attention — a device that is comfortably within spec when warm has its smallest voltage margin when cold.

Voltage spikes in applications and avalanche energy

In a real circuit, a MOSFET sees more than the steady-state bus voltage. Every time it switches off a current, parasitic inductance in the package and PCB traces — or leakage inductance from a transformer, as in a flyback converter — produces a switch-off transient that briefly pushes the drain-source voltage above its steady-state level.

If such a spike exceeds V(BR)DSS, the MOSFET is driven into avalanche — usually a form of unclamped inductive switching (UIS) — and during a high-energy single pulse the clamped voltage typically reaches around 1.3 times V(BR)DSS. A high enough avalanche current can also trigger latch-up in the device's parasitic bipolar transistors, taking the gate out of control. Avalanche is therefore not a recommended operating condition.

It also matters whether avalanche happens once or repeatedly. A single pulse may briefly exceed TJ(max) without permanent damage, but repetitive avalanche is different: each event injects hot carriers that accumulate in the gate oxide and slowly degrade the device — risking a delayed field failure even when every individual pulse looks harmless. An occasional fault-condition avalanche is therefore treated very differently from a design that relies on avalanche as a normal operating mechanism.

Spikes can be reduced by slowing the switch-off through the gate-drive network or by adding an RC snubber across drain and source — both at the cost of extra switching loss. The mechanisms and avalanche specs are covered in detail in the Infineon power MOSFET avalanche design guidelines.

Some datasheets also quantify avalanche directly with an energy rating, EAS — how much energy the device can absorb in a single event. It is defined either as a thermal limit (the energy that raises the junction temperature to TJ(max)) or as a statistical figure (a conservative margin derived from testing many parts to failure).

One caution follows: EAS figures from different manufacturers or test conditions are not directly comparable — the same total energy can produce very different peak junction temperatures depending on the test inductance and starting current, so EAS should always be read together with its test conditions.

Recommended Vds by DC bus voltage

Because of those transients, you never choose a voltage class equal to the bus voltage — you leave headroom. A few widely used rules of thumb:

  • Allow a safety margin of at least 20% between the worst-case steady-state drain-source voltage and the rated V(BR)DSS.
  • A common derating target is to keep the operating voltage at roughly 90% or less of V(BR)DSS.
  • Where large switch-off transients are expected, use a much larger margin. In motor-drive inverters, for instance, it is not unusual to pick a V(BR)DSS rating of about twice the DC bus voltage.

The table below shows typical starting points only — the right class always depends on the real transient behaviour of your circuit:

 

Note: the right-hand column gives typical starting points only. The margin actually required depends on a few factors: your circuit's parasitic inductance, the switching di/dt, and whether snubbing or active gate-drive shaping is used to limit turn-off spikes. Always verify against the real transient behaviour of your design — not just the bus voltage.

Voltage margin, however, isn't the whole safety picture. V(BR)DSS is only one of several limits that define a MOSFET's Safe Operating Area (SOA) — RDS(on), package current handling, power dissipation, and thermal instability all impose their own boundaries, so the SOA diagram in the datasheet gives a fuller picture of safe operation than the voltage rating alone.

It is also a mistake to over-specify. A higher voltage class generally comes with higher on-resistance (RDS(on)) and higher cost, so going further up the voltage ladder than necessary makes the design less efficient and more expensive.

Recommended documents

Frequently asked questions about MOSFET voltage ratings

What are the critical parameters of a MOSFET, including drain current and gate charge?

Beyond the breakdown voltage, a handful of other parameters usually decide a design:

  • RDS(on) — the on-state resistance, which sets conduction loss.
  • VGS(th) — the gate threshold voltage.
  • ID — the maximum drain current, together with the device's thermal limits.
  • Qg — the gate charge, which drives switching loss and gate-drive requirements.
  • The device's parasitic capacitances.
  • gfs — the transconductance, the gain linking drain current to gate voltage. It is typically specified in the saturation region, where the MOSFET behaves as a controlled current source rather than a simple switch.
  • Body-diode behaviour, including reverse recovery (Qrr).

For how these come together in operation, see how does a MOSFET work.

Most power designs use N-channel MOSFETs — and more specifically N-channel enhancement-mode MOSFETs, which are normally off until the gate voltage exceeds the threshold, making them the default choice for switching applications. Depletion-mode devices, by contrast, conduct at zero gate voltage and are normally used only in niche applications.

For a switching converter or motor drive, an enhancement-mode MOSFET operated well outside its saturation region — in the low-resistance ohmic (triode) region — is almost always the right choice.

MOSFET operation modes: enhancement and depletion

MOSFET operation modes: enhancement and depletion

Check two tables on the datasheet. The Absolute Maximum Ratings list the drain-source voltage (VDS) — the voltage class. The Static / Electrical Characteristics give the guaranteed minimum breakdown voltage (V(BR)DSS), measured at VGS = 0 V and a small drain current (often ID = 1 mA) at 25°C.

Remember that the breakdown value is lowest at low temperature, so the 25°C number is the worst case to design against.

Work through the requirements in this order:

  1. Voltage class — with enough margin over worst-case transients.
  2. RDS(on) — for conduction loss.
  3. Current and thermal capability — these depend on the package, thermal resistance, and heatsinking.
  4. Switching characteristics (gate charge, body diode) — matched to your frequency and topology.

Note that the headline ID(max) on a datasheet is based on idealized cooling and should not be taken at face value — judge real current capability from power loss and temperature rise instead.

For switching-specific guidance, see how does a MOSFET work as a switch.

Infineon offers online parametric search and product-finder tools on infineon.com that let you filter MOSFETs by voltage class, RDS(on), package, and application, along with simulation models and selection guides.

For background while you compare parts, the two application notes linked in this article are useful references: the OptiMOS datasheet explanation for reading every spec, and the avalanche design guidelines for voltage-margin and ruggedness decisions.

The OptiMOS™ family and its architecture will be covered in OptiMOS: Infineon's Power MOSFET Family Architecture Explained.

Power MOSFETs come in through-hole packages (such as TO-220 and D²PAK) and a wide range of surface-mount packages (such as SuperSO8/PQFN 5×6, PQFN 3.3x3.3, DirectFET™, and top-side-cooled types like TOLT).

The package affects more than size. It sets the maximum current the part can carry, since bond wires and copper-clip connections handle current differently. It also shapes the parasitic inductance and the cooling path.

Even the maximum junction temperature depends on the package: some compact SMD packages are limited to 150°C, while the same die in a TO-220 or D²PAK may be rated to 175°C.

The continuous drain-current figure ID(max) printed on a datasheet is derived from idealized test conditions (very effective cooling) and usually cannot be reached in a practical design.

A more realistic approach is to size the device by power loss and temperature: combine RDS(on) (and switching loss) with the package's thermal resistance and your heatsinking to confirm that the junction temperature stays below its maximum.

Choosing the part this way — and adding margin — gives a far better picture of real current capability than comparing ID(max) numbers alone.

Not always. There are two distinct failure mechanisms. Thermal failure occurs when the junction temperature reaches the intrinsic temperature of silicon — typically close to 400°C for modern power MOSFET technologies.

Latch-up is a different, often faster mechanism: during avalanche, current flowing through the device's parasitic base resistance can forward-bias the parasitic bipolar transistor built into every MOSFET cell, causing it to turn on uncontrollably and effectively taking the gate out of control.

Latch-up can destroy a device well before thermal failure would occur, which is one reason avalanche should be minimized by design rather than treated as a safety margin to rely on.