S26KS128SDPBHM023
Active and preferred
RoHS Compliant
Lead-free

S26KS128SDPBHM023

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

S26KS128SDPBHM023
S26KS128SDPBHM023


Product details

  • Classification
    ISO 26262-ready
  • Density
    128 MBit
  • Family
    KS-S
  • Initial Access Time
    96 ns
  • Interface Bandwidth
    333 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    - / 166
  • Interfaces
    HYPERBUS
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 125 °C
  • Operating Voltage range
    1.7 V to 1.95 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2035
  • Qualification
    Automotive

OPN
S26KS128SDPBHM023
Product Status active and preferred
Infineon Package
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
ea. in stock

Product Status
Active
Infineon Package
Package Name FBGA-24 (002-15550)
Packing Size 2500
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
The S26KS128SDPBHM023 is a 128 Mb (16 MB) HYPERFLASH™ memory with HYPERBUS™ interface, supporting 1.8 V and 3.0 V operation. It achieves up to 333 MBps DDR read throughput at 166 MHz, features uniform 256 KB sectors, ECC for 1-bit correction, and 20-year data retention. Qualified to AEC-Q100 Grade 1 for -40°C to +125°C, it offers low power modes and 100,000 program/erase cycles, ideal for high-speed automotive and industrial code and data storage.

Features

  • 3.0 V I/O with 11 bus signals
  • 1.8 V I/O with 12 bus signals
  • Up to 333 MBps sustained read throughput
  • DDR: two data transfers per clock
  • 8-bit data bus (DQ[7:0])
  • 96-ns initial random read access time
  • 512-byte program buffer
  • ECC: 1-bit correction, 2-bit detection
  • Hardware accelerated CRC calculation
  • Secure silicon region (1024-byte OTP)
  • Advanced sector protection methods
  • Low power modes: standby 25 µA, deep

Benefits

  • High throughput enables fast data access
  • DDR boosts system performance
  • 8-bit bus simplifies integration
  • Fast random access reduces latency
  • Large buffer speeds up programming
  • ECC ensures reliable data integrity
  • CRC detects data errors quickly
  • Secure region protects critical data
  • Flexible sector protection enhances security
  • Low power modes extend battery life

Applications

Documents

Design resources

Developer community