S25HS512TFAMHB013
Active and preferred
RoHS Compliant
Lead-free

S25HS512TFAMHB013

Data Sheet
package

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S25HS512TFAMHB013
S25HS512TFAMHB013
Data Sheet

Product details

  • Classification
    ISO 26262-compliant
  • Density
    512 MBit
  • Family
    HS-T
  • Interface Bandwidth
    102 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    166 / 102
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Matte Tin Plating
  • Operating Temperature range
    -40 °C to 105 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2037
  • Publish in NPSG
    N
  • Publish in PSG
    N
  • Qualification
    Automotive
Recommended
OPN
S25HS512TFAMHB013
Product Status active and preferred
Infineon Package
PG-DSO-16
Package Name SOIC-16 (002-15547)
Packing Size 1450
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-DSO-16
Package Name SOIC-16 (002-15547)
Packing Size 1450
Packing Type TAPE & REEL
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
S25HS512TFAMHB013 is a 512 Mbit automotive SEMPER™ NOR flash for code and data storage in ECUs. It uses a 1.7 V to 2.0 V supply over -40°C to 105°C and a Quad SPI interface delivering up to 102 MByte/s (166 MHz SDR, 102 MHz DDR). ISO 26262-compliant features include ECC (SECDED), CRC, SafeBoot, and Endurance Flex wear leveling, plus AutoBoot and 4 KB/256 KB erase sectors for flexible updates.

Features

  • 45-nm MIRRORBIT™ 2 bits per cell
  • Uniform or hybrid sector architecture
  • 256 KB sectors plus 32 x 4 KB sectors
  • 256 B or 512 B program buffer
  • Quad SPI: 1-1-4, 1-4-4, 4-4-4
  • Quad SPI DDR read up to 102 MBps
  • Hamming ECC on 16-byte data units
  • SECDED: correct 1-bit, detect 2-bit
  • Memory-array data integrity CRC
  • Endurance Flex wear leveling
  • ASP: DYB/PPB per-sector protection
  • 1024-byte SSR with 32 lock regions

Benefits

  • Higher density lowers board area
  • Match boot+data layout to MCU needs
  • Small sectors enable fine updates
  • Faster writes cut update time
  • Flexible host interface support
  • High read rate speeds code fetch
  • ECC boosts data reliability in field
  • Detects double-bit faults for safety
  • CRC flags corrupted reads early
  • Wear leveling extends flash life
  • Per-sector locks prevent tampering
  • SSR enables IDs and secure storage

Applications

Documents

Design resources

Partner solutions

Developer community

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