S25FS256TDACHC113
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RoHS Compliant

S25FS256TDACHC113

Datasheet
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S25FS256TDACHC113
S25FS256TDACHC113
ea.
Datasheet

Product details

  • Density
    256 MBit
  • Family
    FS-T
  • Interface Bandwidth
    40 MByte/s
  • Interface Frequency (SDR/DDR) (MHz)
    80 / -
  • Interfaces
    Quad SPI
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 2 V
  • Operating Voltage
    1.8 V
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2030
  • Qualification
    Commercial
Recommended
OPN
S25FS256TDACHC113
Product Status active
Infineon Package SG-XFWLB-33
Package Name WLCSP
Packing Size 5000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package SG-XFWLB-33
Package Name WLCSP
Packing Size 5000
Packing Type TAPE & REEL
Moisture Level 1
Moisture Packing NON DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
S25FS256TDACHC113 is a 256 Mbit FS-T NOR Flash for code and data storage over Quad SPI. It operates from 1.7 V to 2.0 V across 0°C to 70°C (commercial) and supports SDR reads up to 80 MHz, with up to 40 MByte/s interface bandwidth. Built-in ECC corrects 1-bit and detects 2-bit errors, with SFDP plus unique ID, RD/BY# status, and RESET#/CS# signaling reset options for robust boot memory.

Features

  • 45-nm MIRRORBIT™ 2-bit-per-cell
  • Uniform 64 KB or 128 KB sectors
  • Configurable sector architecture
  • 256 B or 512 B program buffer
  • SPI 1-1-1 and Quad 1-1-4,1-4-4
  • Up to 104 MHz clock operation
  • ECC on 16-byte data units
  • 1-bit correct, 2-bit detect (ECC)
  • ECC status via EDUS and ECSV regs
  • RD/BY# output for Ready/Busy
  • SafeBoot failure signature in STR1
  • CS# signaling reset + RESET# pin

Benefits

  • 2 bpc lowers cost per stored bit
  • Sector sizes match code vs data
  • Configurable map eases migration
  • Page buffer speeds firmware update
  • Quad I/O enables fast XIP reads
  • 104 MHz supports high throughput
  • ECC improves read data reliability
  • ECC flags speed fault isolation
  • RD/BY# reduces host firmware load
  • SafeBoot enables recovery after fault
  • Reset options improve robustness
  • SFDP support eases host bring-up

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