CY7C4122KV13-106FCXC
Active and preferred
RoHS Compliant
Lead-free

CY7C4122KV13-106FCXC

Datasheet
package

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CY7C4122KV13-106FCXC
CY7C4122KV13-106FCXC
Datasheet


Product details

  • Architecture
    QDR-IV
  • Bank Switching
    Y
  • Burst Length (Words)
    2
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    Y
  • Family
    QDR-IV
  • Frequency
    1066 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.26 V to 1.34 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    8

Recommended
OPN
CY7C4122KV13-106FCXC
Product Status active and preferred
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-FCBGA-361
Package Name FCBGA-361 (001-70319)
Packing Size 600
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C4122KV13-106FCXC is a 144-Mbit QDR-IV XP SRAM (8M × 18) with dual independent bidirectional DDR data ports and a common DDR address bus for concurrent read/write. It supports 2132 MT/s random transaction rate at up to 1066 MHz. The eight-bank, 2-word burst architecture includes on-die termination and per-bit deskew training, plus on-chip ECC and address parity for soft-error protection.

Features

  • 144-Mbit QDR-IV XP SRAM
  • Total RTR 2132 MT/s
  • Max operating frequency 1066 MHz
  • Dual independent bidir DDR ports
  • Single DDR addr bus, SDR control
  • Eight banks, 1 access/bank/cycle
  • Two-word burst for all accesses
  • On-die termination, programmable
  • ZQ self-cal output impedance
  • Bus inversion for addr/data buses
  • Address parity with PE# error flag
  • On-chip ECC, SER <0.01 FIT/Mb

Benefits

  • 2132 MT/s boosts random throughput
  • 1066 MHz enables low-latency ops
  • Concurrent reads/writes on 2 ports
  • Shared addr bus reduces routing
  • 8 banks sustain high transaction rate
  • 2-word burst improves data bandwidth
  • ODT eases signal integrity design
  • ZQ cal keeps stable I/O margins
  • Bus inversion cuts SSN and power
  • Parity flag speeds fault isolation
  • ECC reduces soft-error data faults
  • <0.01 FIT/Mb improves reliability

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