CY7C1618KV18-333BZXC
Active and preferred
RoHS Compliant

CY7C1618KV18-333BZXC

Datasheet
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CY7C1618KV18-333BZXC
CY7C1618KV18-333BZXC
Datasheet

Product details

  • Architecture
    DDR-II CIO
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    N
  • Family
    DDR-II CIO
  • Frequency
    333 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1.5
Recommended
OPN
CY7C1618KV18-333BZXC
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 525
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1618KV18-333BZXC is a 144-Mbit (8M × 18) synchronous pipelined SRAM with a DDR II interface. It supports 333 MHz clocks with double data rate transfers (666 MHz data rate) and a two-word burst counter that uses A0 for burst sequencing. It provides separate K/K and C/C clocks plus CQ/CQ echo clocks for data capture, operates at 1.7 V to 1.9 V VDD with 1.4 V to VDD VDDQ, and comes in a 165-ball Pb-free FBGA.

Features

  • 144-Mbit DDR II synchronous SRAM
  • 333 MHz clock; 666 MHz data rate
  • Two-word burst with 1-bit counter
  • 1.5-cycle latency with DOFF high
  • 1-cycle latency DDR I mode (DOFF)
  • Dual input clocks K/K for DDR
  • Output clocks C/C or single-clock
  • Echo clocks CQ/CQ for data capture
  • Programmable impedance via ZQ pin
  • RQ 175–350 Ω for ±15% match
  • PLL runs 120 MHz to fMAX
  • JTAG IEEE 1149.1 boundary scan

Benefits

  • High bandwidth for fast access
  • More throughput at lower fCLK
  • Less address toggling reduces EMI
  • Latency options ease integration
  • K/K clocks simplify DDR timing
  • C/C clocks help reduce skew
  • CQ/CQ eases high-speed capture
  • ZQ trim improves signal integrity
  • Trace match cuts reflections
  • PLL improves data placement timing
  • JTAG speeds board test and debug
  • Depth expand without added waits

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