CY7C1514KV18-250BZXI
Active and preferred
RoHS Compliant

CY7C1514KV18-250BZXI

package
ea.
in stock

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CY7C1514KV18-250BZXI
CY7C1514KV18-250BZXI
ea.

Product details

  • Density
    72 MBit
  • Family
    QDR-II
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    2M x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
Recommended
OPN
CY7C1514KV18-250BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1514KV18-250BZXI is a 72-Mbit QDR II synchronous pipelined SRAM organized as 2M × 36 with separate read and write ports to eliminate bus turnarounds. It supports two-word burst transfers with DDR I/O (data on both clock edges) and operates at up to 250 MHz clock. Core VDD is 1.8 V ±0.1 V with VDDQ from 1.4 V to VDD. It is offered in a 165-ball FBGA Pb-free industrial option (BZ package).

Features

  • 72-Mbit QDR II SRAM architecture
  • Separate read/write data ports
  • Concurrent read and write transactions
  • Two-word burst on all accesses
  • DDR I/O, 350 MHz (700 MHz data)
  • 1.5-cycle read latency (DOFF=HIGH)
  • 1-cycle read latency (DOFF=LOW)
  • Input clocks K/K and output C/C
  • Echo clocks CQ/CQ for data capture
  • Core VDD 1.7-1.9 V (nom 1.8 V)
  • VDDQ 1.4 V to VDD, VREF range
  • JTAG IEEE 1149.1 boundary scan

Benefits

  • High bandwidth for fast networking
  • No bus turnaround delays
  • Parallel R/W boosts throughput
  • Two-word bursts cut command load
  • DDR at 700 MHz speeds transfers
  • Low-latency reads for tight timing
  • DOFF selects latency vs pipeline
  • Separate clocks ease timing closure
  • Echo clocks simplify PCB capture
  • 1.8 V core helps reduce power
  • HSTL levels fit high-speed links
  • JTAG speeds board test and debug

Applications

Documents

Design resources

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Developer community