CY7C1512KV18-300BZXC
Active and preferred
RoHS Compliant

CY7C1512KV18-300BZXC

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CY7C1512KV18-300BZXC
CY7C1512KV18-300BZXC

Product details

  • Density
    72 MBit
  • Family
    QDR-II
  • Frequency
    300 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4M x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
Recommended
OPN
CY7C1512KV18-300BZXC
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85180)
Packing Size 272
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1512KV18-300BZXC is a 72-Mbit QDR II synchronous pipelined SRAM organized as 4M × 18, with independent read and write ports and two-word burst transfers. It supports DDR I/O for data transfer at 600 MHz with a 300 MHz clock, 1.8 V core supply, and VDDQ from 1.4 V to VDD. It includes 1.5-cycle read latency (DOFF HIGH), byte writes, echo clocks, on-chip PLL, JTAG, and programmable output impedance.

Features

  • 72-Mbit QDR II SRAM architecture
  • Separate read/write data ports
  • Concurrent read and write transactions
  • Two-word burst on all accesses
  • DDR I/O, 350 MHz (700 MHz data)
  • 1.5-cycle read latency (DOFF=HIGH)
  • 1-cycle read latency (DOFF=LOW)
  • Input clocks K/K and output C/C
  • Echo clocks CQ/CQ for data capture
  • Core VDD 1.7-1.9 V (nom 1.8 V)
  • VDDQ 1.4 V to VDD, VREF range
  • JTAG IEEE 1149.1 boundary scan

Benefits

  • High bandwidth for fast networking
  • No bus turnaround delays
  • Parallel R/W boosts throughput
  • Two-word bursts cut command load
  • DDR at 700 MHz speeds transfers
  • Low-latency reads for tight timing
  • DOFF selects latency vs pipeline
  • Separate clocks ease timing closure
  • Echo clocks simplify PCB capture
  • 1.8 V core helps reduce power
  • HSTL levels fit high-speed links
  • JTAG speeds board test and debug

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Documents

Design resources

Partner solutions

Developer community