CY7C1441KV33-133AXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1441KV33-133AXI

Data Sheet
package

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CY7C1441KV33-133AXI
CY7C1441KV33-133AXI
Data Sheet

Product details

  • Architecture
    Standard Sync, Flow-through
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    36 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    133 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Ni/Pd/Au
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.63 V
  • Organization (X x Y)
    1Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Industrial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1441KV33-133AXI
Product Status active and preferred
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-TQFP-100
Package Name TQFP-100 (51-85050)
Packing Size 144
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1441KV33-133AXI is a 36-Mbit synchronous flow-through SRAM organized as 1M × 36 with a user-selectable burst counter (interleaved or linear). It supports 133 MHz operation with 6.5 ns clock-to-output access. The device uses 3.135 V to 3.6 V core (VDD) and 2.5 V or 3.3 V I/O (VDDQ), includes on-chip ECC and ZZ sleep mode, and comes in a 100-pin Pb-free TQFP industrial package.

Features

  • 133 MHz synchronous bus
  • 6.5 ns clock-to-output
  • 3.0 ns OE to output valid
  • 1.5 ns setup to CLK rise
  • 3.3 V core (VDD 3.135-3.6 V)
  • 2.5 V or 3.3 V I/O supply
  • Common I/O: 1M×36 or 2M×18
  • Flow-through synchronous SRAM
  • 2-bit burst counter auto-increment
  • Interleaved or linear burst modes
  • IEEE 1149.1 JTAG boundary scan
  • On-chip ECC for SER reduction

Benefits

  • 133 MHz supports fast CPU buses
  • 6.5 ns cuts read data latency
  • 3.0 ns OE enables fast bus turn
  • 1.5 ns setup eases timing closure
  • 3.3 V core fits common power rails
  • 2.5/3.3 V I/O reduces level shift
  • Common I/O simplifies bus routing
  • Flow-through gives low-latency reads
  • Burst counter reduces glue logic
  • Burst modes match cache-line reads
  • JTAG boundary scan speeds test
  • ECC lowers soft-error field risk

Applications

Documents

Design resources

Partner solutions

Developer community

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