CY7C1440KV33-250BZXI
Active and preferred
RoHS Compliant
Lead-free

CY7C1440KV33-250BZXI

Data Sheet
package
ea.
in stock

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CY7C1440KV33-250BZXI
CY7C1440KV33-250BZXI
ea.
Data Sheet

Product details

  • Architecture
    Standard Sync, Pipeline SCD
  • Bank Switching
    N
  • Data Width
    x 36
  • Density
    36 MBit
  • ECC
    N
  • Family
    Standard Sync
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    3.14 V to 3.6 V
  • Organization (X x Y)
    1Mb x 36
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2031
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1
Recommended
OPN
CY7C1440KV33-250BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1440KV33-250BZXI is a 36-Mbit (1M × 36) pipelined synchronous SRAM for secondary cache, supporting bus operation up to 250 MHz with registered inputs/outputs and 3-1-1-1 burst access. It runs from a 3.3 V core with 2.5 V or 3.3 V I/O, delivers 2.5 ns max clock-to-output (tCO), and offers a user-selectable linear or interleaved burst counter plus ZZ sleep mode and IEEE 1149.1 JTAG boundary scan.

Features

  • Synchronous bus up to 250 MHz
  • Pipelined registered I/O
  • Clock-to-output tCO 2.5 ns
  • 2-bit burst counter, wraparound
  • Interleaved or linear burst modes
  • ADSP and ADSC address strobes
  • Synchronous self-timed writes
  • Byte writes via BWE and BWX
  • Global write (GW) writes all bytes
  • Asynchronous OE tri-states outputs
  • ZZ sleep mode, data retained
  • IEEE 1149.1 JTAG boundary scan

Benefits

  • Supports 250 MHz cache SRAM
  • Higher throughput via pipelining
  • 2.5 ns tCO lowers read latency
  • Burst counter cuts address toggles
  • Fits linear or Pentium burst order
  • Works with CPU or controller bus
  • Self-timed writes ease timing
  • Byte writes cut read-modify-write
  • Global write speeds full-word init
  • OE tri-state enables easy bus share
  • Sleep mode saves power, keeps data
  • JTAG speeds board test and debug

Applications

Documents

Design resources

Partner solutions

Developer community

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