CY7C1061G30-10BV1XI
Active and preferred
RoHS Compliant
Lead-free

CY7C1061G30-10BV1XI

ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1061G30-10BV1XI
CY7C1061G30-10BV1XI
ea.


Product details

  • Density
    16 MBit
  • Family
    FAST SRAM
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage (VCCQ) range
    2.2 V to 3.6 V
  • Operating Voltage range
    2.2 V to 3.6 V
  • Organization (X x Y)
    1M x 16
  • Peak Reflow Temp
    260 °C
  • Planned to be available until at least
    2033
  • Qualification
    Industrial
  • Speed
    10 ns

OPN
CY7C1061G30-10BV1XI
Product Status active and preferred
Infineon Package
Package Name VFBGA-48 (51-85150)
Packing Size 480
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free Yes
Halogen Free Yes
RoHS Compliant Yes
Infineon stock last updated:
ea. in stock

Product Status
Active
Infineon Package
Package Name VFBGA-48 (51-85150)
Packing Size 480
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C1061G30-10BV1XI is a 16-Mbit (1M x 16) asynchronous SRAM with embedded ECC for single-bit error correction. It operates from 2.2 V to 3.6 V and is specified for 10 ns address access. Byte writes are supported via BLE/BHE and a single chip enable, with TTL-compatible I/O. Industrial operation is -40°C to 85°C, with ICC 110 mA max at 100 MHz and ISB2 30 mA max standby. Offered in a 48-ball VFBGA.

Features

  • 16-Mbit (1M x 16) async SRAM
  • Embedded ECC single-bit correction
  • ERR output flags corrected 1-bit
  • tAA access time 10 ns/15 ns
  • 16-bit I/O with BLE/BHE byte writes
  • Single or dual chip-enable inputs
  • Auto CE power-down (ISB1/ISB2)
  • ICC typ 90 mA at 100 MHz
  • 1.0 V data retention mode
  • TTL-compatible I/O levels
  • Ambient temp -40°C to +85°C
  • ESD > 2001 V (MIL-STD-883)

Benefits

  • ECC improves SRAM data integrity
  • ERR pin simplifies error monitoring
  • 10 ns access supports fast reads
  • Byte writes reduce write bandwidth
  • CE options ease system integration
  • Auto power-down cuts standby draw
  • 1.0 V retention lowers backup power
  • TTL levels ease bus interfacing
  • -40°C to +85°C boosts reliability
  • High ESD improves handling margin
  • Lower active current reduces heat
  • Async SRAM simplifies controller logic

Applications

Documents

Design resources

Developer community