PSoC® 4100/4200

Key features:

32-Bit MCU Subsystem:

• 48MHz Arm® Cortex®-M0 CPU
• Up to 32KB Flash with Read Accelerator
• Up to 4KB SRAM 

Programmable Analog:

• One 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer
• One opamp configurable as a programmable gain amplifier (PGA), trans-impedance amplifier, voltage buffer, filter, comparator, etc. 
• Two low-power comparators (CMPs) that operate in Deep Sleep low-power mode
• Two 7-bit current-output digital-to-analog converters (IDAC) configurable as a single 8-bit IDAC, for general-purpose or capacitive sensing 

Programmable Digital:

• Four programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital blocks or UDBs)

Low Power 1.71V to 5.5V Operation:

• 20-nA Stop Mode with GPIO pin wakeup
• Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs

Capacitive Sensing:

• Cypress Capacitive Sigma-Delta (CSD) provides best-in-class signal-to-noise ratio (SNR) and water tolerance 

Serial Communication:

• Two independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI, UART, or LIN Slave functionality

Timing and Pulse-Width Modulation: 

• Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks
• Center-aligned, Edge, and Pseudo-random modes
• Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications

LCD Drive Capability:

• LCD segment drive capability on GPIOs

Up to 24 GPIO Pins:

• 28-pin SSOP package

Temperature Ranges: 

• Automotive Electronics Council (AEC) AEC-Q100 Qualified
• A Grade: -40°C to +85°C
• S Grade: -40°C to +105°C 

Development Tools:

• PSoC Creator design environment providing an Integrated Development Environment (IDE) including schematic design entry and build (with analog and digital routing)
• Industry-standard tool compatibility, after schematic entry, development can be done with Arm-based industry-standard development tools