CY7C2663KV18-450BZI
Active and preferred

CY7C2663KV18-450BZI

Data Sheet
package
ea.
in stock

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C2663KV18-450BZI
CY7C2663KV18-450BZI
ea.
Data Sheet

Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    450 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2.5
Recommended
OPN
CY7C2663KV18-450BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
ea.
in stock
CY7C2663KV18-450BZI is a 144-Mbit QDR II+ synchronous pipelined SRAM in an 8M × 18 organization with separate read and write ports for concurrent transactions. It supports 2.5-cycle read latency, four-word burst, and DDR I/O (data transfer at 1100 MHz) with a 450 MHz max clock. Operates at VDD 1.7–1.9 V and VDDQ 1.4 V to VDD, with ODT and echo clocks (CQ/CQ) in a 165-ball FBGA, industrial -40 to 85°C.

Features

  • QDR II+ SRAM, 4-word burst
  • 550 MHz clock, 1100 MHz DDR data
  • Separate read/write data ports
  • Supports concurrent transactions
  • 2.5-cycle read latency (DOFF=1)
  • 1-cycle read latency mode (DOFF=0)
  • On-die termination for D/BWS/K
  • Echo clocks (CQ/CQ) for capture
  • QVLD pin indicates valid output data
  • PLL locks with 20 µs stable clock
  • PLL operates down to 120 MHz
  • VDD 1.7–1.9 V; VDDQ 1.4 V–VDD

Benefits

  • High bandwidth with fewer addresses
  • Faster transfers at 1100 MHz DDR
  • No bus turnarounds, lower latency
  • Read+write same time boosts throughput
  • Predictable 2.5-cycle read timing
  • 1-cycle reads cut access delay
  • ODT reduces external termination BOM
  • CQ/CQ eases timing at high speed
  • QVLD simplifies receive data capture
  • PLL stabilizes data placement
  • Runs PLL even at 120 MHz clocks
  • Works with 1.4 V or 1.5 V I/O

Applications

Documents

Design resources

Partner solutions

Developer community

{ "ctalist":[ { "link" : "https://community.infineon.com/t5/forums/postpage/choose-node/true", "label" : "Ask the community", "labelEn" : "Ask the community" }, { "link" : "https://community.infineon.com/t5/Forums/ct-p/products", "label" : "View all discussions", "labelEn" : "View all discussions" } ] }