CY7C2644KV18-300BZXI
Active and preferred
RoHS Compliant

CY7C2644KV18-300BZXI

Datasheet
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CY7C2644KV18-300BZXI
CY7C2644KV18-300BZXI
Datasheet


Product details

  • Architecture
    QDR-II+, ODT
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 36
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+, ODT
  • Frequency
    300 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    Y
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    4Mb x 36
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2.5

Recommended
OPN
CY7C2644KV18-300BZXI
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:
 ea. in stock

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 105
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C2644KV18-300BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM with separate read and write ports and a two-word burst architecture. It transfers data on both edges of K/K clocks (DDR, 500 MHz at 250 MHz) with 2.0-cycle read latency, echo clocks (CQ/CQ), QVLD, and on-die termination for D, BWS, and K/K. It runs from 1.8 V core (VDD 1.7–1.9 V) and 1.4 V to VDD I/O (VDDQ), in a 165-ball CCGA.

Features

  • QDR II+ dual-port read/write
  • Two-word burst per address
  • DDR I/O at 250 MHz (500 MHz)
  • Separate D and Q buses (no turn)
  • 2-cycle read latency (DOFF high)
  • QDR I mode, 1-cycle read latency
  • ODT for D/BWS and K/K inputs
  • Echo clocks CQ/CQ for capture
  • QVLD indicates valid output data
  • PLL runs 120 MHz to 250 MHz
  • ZQ resistor sets driver impedance
  • VDD 1.7–1.9 V; VDDQ 1.4 V–VDD

Benefits

  • Full-duplex access boosts bandwidth
  • Burst cuts address bus frequency
  • 250 MHz interface meets fast links
  • No turnaround prevents contention
  • 2-cycle latency eases timing closure
  • QDR I mode supports legacy timing
  • ODT reduces external resistor BOM
  • CQ/CQ simplify high-speed capture
  • QVLD improves read data confidence
  • PLL tightens output timing margins
  • Impedance match reduces ringing
  • VDD/VDDQ range eases power design

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