CY7C1643KV18-450BZI
Active and preferred

CY7C1643KV18-450BZI

Data Sheet
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CY7C1643KV18-450BZI
CY7C1643KV18-450BZI
Data Sheet

Product details

  • Architecture
    QDR-II+
  • Bank Switching
    N
  • Burst Length (Words)
    4
  • Data Width
    x 18
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II+
  • Frequency
    450 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Pb
  • On-Die Termination
    N
  • Operating Temperature range
    -40 °C to 85 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    8Mb x 18
  • Peak Reflow Temp
    260 °C
  • Qualification
    Industrial
  • Read Latency (Cycles)
    2
Recommended
OPN
CY7C1643KV18-450BZI
Product Status active and preferred
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free Yes
RoHS Compliant No
Infineon stock last updated:

Product Status
Active
Infineon Package
P-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 210
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1643KV18-450BZI is a 144-Mbit QDR II+ synchronous pipelined SRAM (8 M × 18) with separate read and write ports and four-word burst operation. It supports 450 MHz clocks with DDR transfers (900 MHz data rate) and 2.0-cycle read latency. The device runs from 1.7–1.9 V core (VDD) with 1.4 V–VDD I/O (VDDQ) over the industrial range of -40 to +85°C in a 165-ball FBGA, and is JTAG 1149.1 compatible.

Features

  • 144-Mbit QDR II+ burst SRAM
  • Separate read and write ports
  • DDR I/O; data at 900 MHz max
  • 450 MHz max clock frequency
  • Four-word burst per access
  • Read latency 2 cycles (DOFF high)
  • QDR I mode: 1-cycle latency (DOFF)
  • Two input clocks K and K
  • Echo clocks CQ and CQ
  • QVLD valid-data output
  • PLL locks after 20 µs stable clock
  • Programmable output impedance (ZQ)

Benefits

  • Eliminates bus turnaround delays
  • Enables high memory bandwidth
  • Cuts address bus frequency needs
  • Simplifies timing with echo clocks
  • Easier data capture with QVLD
  • Pipelines read/write independently
  • Supports read-after-write coherency
  • Adapts to line impedance for SI
  • Reduces board tuning across PVT
  • Faster bring-up via auto PLL lock
  • Depth expansion without wait states
  • Simplifies test with JTAG port

Applications

Documents

Design resources

Partner solutions

Developer community

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