CY7C1625KV18-250BZXC
Active and preferred
RoHS Compliant

CY7C1625KV18-250BZXC

package

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CY7C1625KV18-250BZXC
CY7C1625KV18-250BZXC

Product details

  • Architecture
    QDR-II
  • Bank Switching
    N
  • Burst Length (Words)
    2
  • Data Width
    x 9
  • Density
    144 MBit
  • ECC
    N
  • Family
    QDR-II
  • Frequency
    250 MHz
  • Interfaces
    Parallel
  • Lead Ball Finish
    Sn/Ag/Cu
  • On-Die Termination
    N
  • Operating Temperature range
    0 °C to 70 °C
  • Operating Voltage range
    1.7 V to 1.9 V
  • Organization (X x Y)
    16Mb x 9
  • Peak Reflow Temp
    260 °C
  • Qualification
    Commercial
  • Read Latency (Cycles)
    1.5
Recommended
OPN
CY7C1625KV18-250BZXC
Product Status active and preferred
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 1050
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead-free No
Halogen Free No
RoHS Compliant Yes
Infineon stock last updated:

Product Status
Active
Infineon Package
PG-BGA-165
Package Name FBGA-165 (51-85195)
Packing Size 1050
Packing Type TRAY
Moisture Level 3
Moisture Packing DRY
Lead Free
Halogen Free
RoHS Compliant
CY7C1625KV18-250BZXC is a 144-Mbit QDR II synchronous pipelined SRAM in a 165-ball FBGA. It implements separate read and write ports with two-word burst transfers (16M × 9 organization) and DDR data interfaces. Rated for 250 MHz operation, it supports 1.5-cycle read latency in QDR II mode (DOFF high) or 1-cycle latency in QDR I mode (DOFF low), with echo clocks, ZQ programmable impedance and on-chip PLL.

Features

  • Dual read/write data ports
  • 360 MHz clock operation
  • DDR I/O, 720 MHz data transfer
  • Two-word burst on all accesses
  • Two input clocks K and K
  • Separate output clocks C and C
  • Echo clocks CQ and CQ
  • 1.5-cycle read latency (DOFF=1)
  • 1-cycle read latency (DOFF=0)
  • 1.8 V VDD supply
  • VDDQ = 1.4 V to VDD
  • IEEE 1149.1-2001 JTAG TAP

Benefits

  • No bus turnaround, more bandwidth
  • Concurrent reads and writes
  • Fast throughput at 360 MHz
  • Echo clocks ease data capture
  • C/C clocks reduce skew issues
  • Flexible latency eases timing
  • PLL improves data placement
  • JTAG simplifies board test
  • Port selects enable depth scaling
  • VDDQ range eases I/O matching
  • Defined power-up prevents faults
  • Low SER improves data integrity

Applications

Documents

Design resources

Partner solutions

Developer community

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